Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-01-08
2001-12-11
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S004000, C438S014000
Reexamination Certificate
active
06329212
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to analysis of semiconductor die, and more particularly to providing access to the back side of a packaged semiconductor die.
BACKGROUND
The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past the die and package were first attached and then the electrical connections from the die to the package were made by wire bonding. The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action was to bond the wire to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding was critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make a good electrical contact at both ends, span between the pad and the inner lead in a prescribed loop without kinks, and be at a safe distance from neighboring lead wires. Wire loops in these packages are 8 to 12 mils, while those of ultra-thin packages are 4 to 5 mils. Wire bonding has been done with either gold or aluminum wires. Both types of wire are highly conductive and ductile enough to withstand deformation during the bonding steps and remain strong and reliable.
Wire bonding between a die and a package has several problems. One problem is that a wire bond attachment to a die limits the number of pads and placement of the pads on the die. In addition, minimum height limits are imposed by the required wire loops. Another problem is that there is a chance of electrical performance problems or shorting if the wires come too close to each other. The wire bonds also require two bonds and must be placed one-by-one and there are resistance levels associated with each bond. The wires are also relatively long and thus could contribute significantly to lead inductance and capacitance. This could limit acceptable signal speed in the system.
To increase the number of pad sites available for a die and to address the problems stated above and other problems, a different chip packaging technique called controlled collapse chip connection or flip chip packaging is being adopted. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Alternatively, the output terminals of the package may be pins and such a package is commonly known as pin grid array (PGA) package.
In one type of package for a flip-chip, a ceramic package has a cavity in which the flip-chip is mounted. The backside of the die is mounted to a die paddle, and the die paddle is mounted in the cavity. Metal leads from the ceramic package can then be attached to the flip-chip. From a die analysis standpoint, a problem created by this type of package is that both the circuit side and back side of the die are covered. Thus, the structure prevents quality assurance and failure analysis of the packaged die. Therefore, it would be desirable to have a process to expose the back side of the die.
SUMMARY OF THE INVENTION
In an example embodiment, a method is provided for preparing a die in a package for analysis. The method comprises removing a selected portion of the package, whereby a selected area of the die is exposed and a cavity is formed in the package. Thereafter, a selected portion the die at the exposed area is removed. In a final phase, the exposed surface of the die is polished.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5424254 (1995-06-01), Damiot
patent: 5698474 (1997-12-01), Hurley
patent: 5700697 (1997-12-01), Dlugokecki
patent: 5930588 (1999-07-01), Paniccia
patent: 5963781 (1999-10-01), Winer
patent: 5972725 (1999-10-01), Wollesen et al.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Ha Nathan W.
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