Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly alloy coating
Reexamination Certificate
1999-08-31
2001-11-20
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly alloy coating
C205S106000, C205S123000, C205S239000
Reexamination Certificate
active
06319387
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices which may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. The metallization used to form such interconnects likewise has applicability in the formation of discrete microelectronic components, such as read/write heads, on other substrate materials. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
Delays in propagation of electrical signals between devices on a single dice limit the performance of integrated circuits. Such delays in propagation also limit the performance of discrete microelectronic components. More particularly, these delays limit the speed at which an integrated circuit or microelectronic component may process or otherwise conduct these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
For each interconnect path, signal propagation delay may be characterized by a time delay &tgr;. See E. H. Stevens,
Interconnect Technology,
QMC, Inc., July 1993. An approximate expression for the time delay, &tgr;, as it relates to the transmission of a signal between transistors on an integrated circuit is given by the equation:
&tgr;=RC
[1+(
V
SAT/
/RI
SAT
)]
In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path, and I
SAT
and V
SAT
are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, &rgr;, of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, K
e
, of the dielectric material. A small value of &tgr; requires that the interconnect line carry a current density sufficiently large to make the ratio V
SAT/
/RI
SAT
small. It follows, therefore, that a low-&rgr; conductor that can carry a high current density and a low-K
e
dielectric should be utilized in the manufacture of high-performance integrated circuits.
To meet the foregoing criterion, copper interconnect lines within a low-K
e
dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to Follow”,
Semiconductor International,
November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 &mgr;&OHgr;cm. while resistivities of aluminum-alloy films are higher in the range of 3.0 to 3.5 &mgr;&OHgr;cm.
Despite the advantageous properties of copper, several problems must be addressed for copper interconnects to become viable in large-scale manufacturing processes.
Diffusion of copper is one such problem. Under the influence of an electric field, and at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper also moves rapidly through low-K
e
dielectrics. Such copper diffusion causes failure of devices formed within the silicon.
Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed to an oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when compared to a similarly dimensioned non-oxidized copper path.
A still further problem with using copper in integrated circuits is that it is difficult to use copper in a multi-layer, integrated circuit structure with dielectric materials. Using traditional methods of copper deposition, copper adheres only weakly to dielectric materials.
Finally, because copper does not form volatile halide compounds, direct plasma etching of copper cannot be employed in fine-line patterning of copper. As such, copper is difficult to use in the increasingly small geometries required for advanced integrated circuit devices.
The semiconductor industry has addressed some of the foregoing problems and has adopted a generally standard interconnect architecture for copper interconnects. To this end, the industry has found that fine-line patterning of copper can be accomplished by etching trenches and vias in a dielectric, filling the trenches and vias with a deposition of copper, and removing copper from above the top surface of the dielectric by chemical-mechanical polishing (CMP). An interconnect architecture called dual damascene can be employed to implement such an interconnect structure and thereby form copper lines within a dielectric.
At least one of the processes in the formation of the dual-damascene architecture is particularly troublesome. More particularly, deposition of thin, uniform barrier and seed layers into high aspect ratio (depth/diameter) vias and high aspect ratio (depth/width) trenches is difficult. The upper portions of such trenches and vias tend to pinch-off before the respective trench and/or via is completely filled or layered with the desired material. This problem is further exacerbated when the interconnect structures formed in the trenches and vias include multiple layers. Conductivities of known barrier materials are negligible compared to the conductivity of copper, thus the conductance of narrow interconnect lines is markedly reduced by the barrier layer that must be interposed between the copper and dielectric.
The present inventors have found that deposition of lean alloys of copper may solve these problems. More particularly, the present inventors have determined that addition of zinc to copper in very low quantities assists in solving the diffusion and self-passivation problems and, further, have suggested a metallization structure that takes advantage of these qualities. Still further, the present inventors have developed an electroplating process that may be used to deposit the copper/zinc alloy that may be used in conjunction with the other processes employed to form the proposed metallization structure.
BRIEF SUMMARY OF THE INVENTION
A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent. preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.
REFERENCES:
patent: 3878066 (1975-04-01),
Duquette David J.
Krishnamoorthy Ahila
Murarka Shyam P.
Christensen O'Connor Johnson & Kindness PLLC
Gorgos Kathryn
Leader William T.
Semitool Inc.
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