Chemistry of inorganic compounds – Silicon or compound thereof – Elemental silicon
Reexamination Certificate
1998-04-09
2001-02-20
Jones, Deborah (Department: 1775)
Chemistry of inorganic compounds
Silicon or compound thereof
Elemental silicon
C428S312600, C428S064100, C118S900000
Reexamination Certificate
active
06190631
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a silicon wafer, and a process for the preparation thereof, which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects.
Single crystal silicon, which is the starting material for most processes for the fabrication of semiconductor electronic components, is commonly prepared with the so-called Czochralski process wherein a single seed crystal is immersed into molten silicon and then grown by slow extraction. As molten silicon is contained in a quartz crucible, it is contaminated with various impurities, among which is mainly oxygen. At the temperature of the silicon molten mass, oxygen comes into the crystal lattice until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in solidified silicon. Such concentrations are greater than the solubility of oxygen in solid silicon at the temperatures typical for the processes for the fabrication of electronic devices. As the crystal grows from the molten mass and cools, therefore, the solubility of oxygen in it decreases rapidly, whereby in the resulting slices or wafers, oxygen is present in supersaturated concentrations.
Thermal treatment cycles which are typically employed in the fabrication of electronic devices can cause the precipitation of oxygen in silicon wafers which are supersaturated in oxygen. Depending upon their location in the wafer, the precipitates can be harmful or beneficial. Oxygen precipitates located in the active device region of the wafer can impair the operation of the device. Oxygen precipitates located in the bulk of the wafer, however, are capable of trapping undesired metal impurities that may come into contact with the wafer. The use of oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to as internal or intrinsic gettering (“IG”).
Historically, electronic device fabrication processes included a series of steps which were designed to produce silicon having a zone or region near the surface of the wafer which is free of oxygen precipitates (commonly referred to as a “denuded zone” or a “precipitate free zone”) with the balance of the wafer, i.e., the wafer bulk, containing a sufficient number of oxygen precipitates for IG purposes. Denuded zones can be formed, for example, in a high-low-high thermal sequence such as (a) oxygen out-diffusion heat treatment at a high temperature (>1100° C.) in an inert ambient for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600-750° C.), and (c) growth of oxygen (SiO
2
) precipitates at a high temperature (1000-1150° C.). See, e.g., F. Shimura,
Semiconductor Silicon Crystal Technology
, Academic Press, Inc., San Diego Calif. (1989) at pages 361-367 and the references cited therein.
More recently, however, advanced electronic device manufacturing processes such as DRAM manufacturing processes have begun to minimize the use of high temperature process steps. Although some of these processes retain enough of the high temperature process steps to produce a denuded zone and sufficient density of bulk precipitates, the tolerances on the material are too tight to render it a commercially viable product. Other current highly advanced electronic device manufacturing processes contain no out-diffusion steps at all. Because of the problems associated with oxygen precipitates in the active device region, therefore, these electronic device fabricators must use silicon wafers which are incapable of forming oxygen precipitates anywhere in the wafer under their process conditions. As a result, all IG potential is lost.
SUMMARY OF THE INVENTION
Among the objects of the invention, therefore, is the provision of a single crystal silicon wafer which, during the heat treatment cycles of essentially any electronic device manufacturing process, will form an ideal, non-uniform depth distribution of oxygen precipitates; the provision of such a wafer which will optimally and reproducibly form a denuded zone of sufficient depth and a sufficient density of oxygen precipitates in the wafer bulk; the provision of such a wafer in which the formation of the denuded zone and the formation of the oxygen precipitates in the wafer bulk is not dependant upon differences in oxygen concentration in these regions of the wafer; the provision of such a process in which the formation of the denuded zone does not depend upon the out-diffusion of oxygen; the provision of such a wafer in which the thickness of the resulting denuded zone is essentially independent of the details of the IC manufacturing process sequence; the provision of such a wafer in which the formation of the denuded zone and the formation of the oxygen precipitates in the wafer bulk is not influenced by the thermal history and the oxygen concentration of the Czochralski-grown, single crystal silicon ingot from which the silicon wafer is sliced; and, the provision of such a wafer which additionally contains an axially symmetric region of substantial radial width which is substantially free of defects resulting from the agglomeration of crystal lattice vacancies or silicon self-interstitials.
Briefly, therefore, the present invention is directed to a single crystal silicon wafer having two major, generally parallel surfaces, one of which is the front surface of the wafer and the other of which is the back surface of the wafer, a central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, a surface layer which comprises the region of the wafer between the front surface and a distance, D
1
, of at least about 10 micrometers measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the wafer between the central plane and the first region. In particular, the wafer has a non-uniform distribution of crystal lattice vacancies, with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer and with the vacancies having a concentration profile in which the peak density of the vacancies is at or near the central plane, the concentration generally decreasing from the position of peak density in the direction of the front surface of the wafer. In one embodiment, the wafer additionally has a first axially symmetric region in which vacancies are the predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects, wherein the first axially symmetric region comprises a central axis or has a width of at least about 15 mm. In another embodiment, the wafer additionally has an axially symmetric region which is substantially free of agglomerated intrinsic point defects, the axially symmetric region extending radially inwardly from the circumferential edge of the wafer and having a width, as measured from the circumferential edge radially toward a center axis, which is at least about 40% the length of a radius of the wafer.
The present invention is further directed to a single crystal silicon wafer comprising two major, generally parallel surfaces, one of which is the front surface of the wafer and the other of which is the back surface of the wafer, a central plane between the front and back surfaces, and a circumferential edge joining the front and back surfaces, a front surface layer consisting of the region of the wafer within a distance, D
2
, of no more than about 15 micrometers of the front surface and a bulk layer comprising the region of the wafe
Cornara Marco
Falster Robert A.
Gambaro Daniela
Holzer Joseph C.
Johnson Bayard K.
Jones Deborah
MEMC Electronic Materials , Inc.
Senniger Powers Leavitt & Roedel
Stein Stephen
LandOfFree
Low defect density, ideal oxygen precipitating silicon does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low defect density, ideal oxygen precipitating silicon, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low defect density, ideal oxygen precipitating silicon will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2582038