Passivation layer for packaged integrated circuits

Details Passivation layer for packaged integrated circuits Passivation layer for packaged integrated circuits

1999-09-08

2001-11-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S127000

Reexamination Certificate

active

06316285

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to passivation layers for packaged dies and methods for forming the same.
2. Description of the Related Art
Die carriers are used in the construction of integrated circuit chips or dies to connect such dies to larger circuits, such as the motherboard of personal computers. In the past, die carriers, such as lead frames, have been most commonly metal. After mounting the die of the die carrier and connecting the leads, passivation layers are generally formed over the mounted die and carrier to protect the chips from moisture, chemicals, and other environmental factors.
Passivation layers can be formed on lead frames using chemical-vapor deposition and thermal processes at relatively high temperatures, due to the high melting point of the metal. Recently, however, plastic has become more widely used in die carriers. Due to the low melting point of plastics, such die carriers are easily damaged by exposure to high temperature steps.
Consequently, there is a need for a process for forming a protective layer on integrated circuit devices and other surface mounted structures at lower temperatures. Desirably, the passivation layers formed by the process should be moisture resistant and protect the underlying die.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a process for forming a passivated integrated circuit device is provided. The process includes mounting a die onto a surface of a die carrier. An organosilane precursor is reacted to form a layer of photosensitive material on surfaces of the die and the die carrier.
In accordance with another aspect of the invention, a method is disclosed for packaging an integrated circuit die to form a surface mount device. The method involves mounting the die onto a surface of a plastic die carrier. A photodefinable layer is deposited on the die and the die carrier after mounting the die. This photodefinable is then converted to a passivation layer.
In accordance with another aspect of the invention, a method is provided for packaging an integrated circuit die for surface mounting. The die is mounted on a die carrier. A layer of plasma polymerized methylsilane (PPMS) is deposited onto a first side of the die and die carrier after mounting the die. At least a portion of the PPMS is then exposed to ultraviolet (UV) light in the presence of oxygen.
In accordance with still another aspect of the invention, a packaged integrated circuit device is provides. The device includes a die carrier, with an integrated circuit die mounted onto a surface of the die carrier. A passivation layer, including plasma polymerized methylsiloxane (PPMSO), extends over portions of the die and the die carrier.
In an illustrative embodiment of the invention, reacting methylsilane in a plasma enhanced CVD reactor leaves a layer of PPMS. Advantageously, this layer is formed at low temperatures, and then converted by exposure to UV light to the oxide-like passivation layer of PPMSO. The low temperatures of the process enables passivation of die carriers having plastic substrates, such as a plastic ball grid array.


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