Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
2000-04-18
2001-10-09
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
C341S069000
Reexamination Certificate
active
06300886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to optical disc recording or playing systems and, more particularly, to a method of and a system for modulating a 4-bit data sequence into a 6-bit code stream based on (1, 7) run-length-limited (RLL) constraints for digital data recording on an optical disc and to a demodulation method and system adapted for the modulation method and system.
2. Description of the Prior Art
In recording on the optical disc or the magnetic disc, a channel coding or modulation scheme known as (1, 7) run-length-limited (RLL) constraints is widely used in view of optical transmission characteristics in recording and reading and physical restrictions involved in pit formation. In the channel coding, for the sake of servo control, the digital sum value (DSV) is controlled so as to satisfy a constraint on low-frequency components as is well known in the art. However, conventional (1, 7) RLL scheme can not afford a satisfactory control of the DSV to some bit patterns to fail in suppression of DC components, resulting in, for example, information signal components mixing in the servo signal band. This presumably causes a problem of adversely affecting the servo performance.
From this point of view, Japanese unexamined patent publication No. 06195887 (1994) discloses “Recording Sign Modulating Device,” in which a suggestion is provided to reduce a DC component by avoiding repetition of a specific bit pattern.
Japanese unexamined patent publication No. 10340543 (1998) discloses “Encoding Device, Decoding Device, Encoding Method and Decoding Method Therefore,” in which a suggestion is provided to reduce a DC component by inserting a DSV control code by a number of bits having a redundancy as less as possible.
Though the publication No. 06195887 can reduce repetition of a specific bit pattern through bit inversion and/or making patterns random but can hardly suppress a DC component to a satisfactory extent. The publication No. 10340543 seems to provide a preferable DC suppression result but at the same time lowers the storage capacity due to insertion of DSV control codes.
It is therefore an object of the invention to provide a four-to-six modulation code system (or table), and a four-to-six modulation method and system that uses the modulation code table to provides a 6-bit code stream satisfying the (1, 7) RLL and DSV constraints without the need of merging bit or DSV control bit.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a code table system for use in converting each input code of a 4-bit input code sequence into a 6-bit output code whose NRZI-converted version satisfies (1, 7) run-length-limited (RLL) constraints in a 4-to-6 modulator which simply concatenates the converted 6-bit output codes into a 6-bit output code sequence that still satisfies the run-length limited constraints. The code table system comprises a column for storing 2
4
possible 4-bit input codes in order of magnitude; and a plurality of columns (hereinafter referred to as “tables”). Each table comprises a table ID for identifying the table and 2
4
combinations of 6-bit output codes and respective next table fields which combinations are associated in the row directions with respective input codes. Each of the next table fields contains a table ID of a table to be used in a modulation of a next source of the input code sequence so as to cause the input code sequence to satisfy the RLL constraints. Output codes are permitted to appear repeatedly in the 6-bit output codes in each table such that combinations of appearances of each of the repeated output codes and respective next table fields are unique in the table. If one of predetermined patterns of three consecutive input codes is to be coded and if a third input code of the one predetermined pattern is in a predetermined input code range, then an output code associated with the third input code in an original table specified by a next table field associated with a second input code of the one predetermined pattern can be replaced with a corresponding output code in an alternative table assigned to the one predetermined pattern. The odd/even property of output codes of the original table which correspond to the predetermined input code range is different from that of output codes of the alternative table which correspond to the predetermined input code range.
According to another aspect of the invention, a method of and a system for modulating a 4-bit input code sequence into a 6-bit output code sequence which includes no merging bit and whose NRZI converted version satisfies (1, 7) run-length-limited constraints is provided. The method and system use the above-described code system. A first output code associated with an input code of the input code sequence is retrieved from a table identified by a next table field attached to the last modulated output code. A test is made to see if the input code and the two input codes following the input code in the input code sequence coincide with any of the predetermined pattern. In response to a pass in the test, a second output code associated with the input code of the input code sequence is retrieved from the alternative table. A first digital sum value (DSV) and a second DSV are calculated by using the first output code and the second output code, respectively. If the absolute value of the second DSV is smaller than that of the first DSV, then the second output code is included in the 6-bit output code sequence. If the test is unsuccessful or if the absolute of the second DSV is not smaller than that of the first DSV, the first output code is included in the 6-bit output code sequence.
According to further aspect of the invention, a method of and system for demodulating a 6-bit code sequence into a 4-bit code sequence in a 6-to-4 demodulator is provided. The demodulator is provided with a decoding table for associating each of possible 6-bit current codes with an indicator and corresponding 4-bit codes further associated with respective table ID's for use in a demodulation of a next 6-bit code following a current 6-bit code. The indicator indicates a table list listing ID's of tables that might be used for coding of the next 6-bit code. The demodulator further comprises means for associating a 6-bit code with at least one coding table ID from which the 6-bit code can be derived. The indicator and the corresponding 4-bit codes are found from the decoding table by using the current 6-bit code. At least one coding table ID for the next 6-bit code is obtained from the means by using the next 6-bit code. As a next table ID for the next 6-bit code, a table ID common to the at least one coding table ID and table ID's listed in the table list indicated by the indicator is found. A 4-bit code associated with the current 6-bit code and the common table ID is obtained and output.
According to an aspect of the invention, an optical disc storing an NRZI converted version of a 6-bit output code sequence is provided. The output code sequence is obtained through a method of modulating a 4-bit input code sequence into the 6-bit output code sequence which includes no merging bit and whose NRZI converted version satisfies (1, 7) run-length-limited constraints in a 4-to-6 modulator. The modulator is provided with the above-described code table. The method comprises the steps of retrieving a first output code associated with an input code of the input code sequence from a table identified by a next table field attached to the last modulated output code; making a test to see if the input code and the two input code following the input code in the input code sequence coincide with any of the predetermined pattern; in response to a pass in the test, retrieving a second output code associated with the input code of the input code sequence from the alternative table; calculating a first digital sum value (DSV) and a second DSV by using the first output code and the second output code, respectively; if the absolute value
Lowe Hauptman & Gilman & Berner LLP
Victor Company of Japan Ltd.
Williams Howard L.
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