Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-02-03
2001-02-27
Saras, Steven J. (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S213000
Reexamination Certificate
active
06195071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flat panel display apparatus and, more particularly, to a timing control circuit of a plasma display panel (PDP) television which generates clock signals to control input/output operations of a video data to/from a data interfacing circuit.
2. Description of the Prior Art
A PDP system can be classified into an alternating current (AC) type and a direct current (DC) type according to kinds of driving voltages being applied to discharge cells. In
FIG. 1
, a whole circuit configuration of an AC type PDP color television which relates to the present invention is illustrated. In the AC type PDP color television, a composite video signal received through an antenna is converted into a digital data by an analog-to digital converting section
12
after being processed by an audio/video signal processing section
10
. Here, one frame of the composite video signal consists of two fields, that is, an even field and an odd field which are being interlaced, and a horizontal sync signal has a frequency of about 15.73 Khz and a vertical sync signal has a frequency of about 60 Hz. After being processed by a data processing section
14
which contains a data rearranging section
14
a
, a frame memory section
14
b
and a data interfacing section
14
c
, the digital data is transferred to address electrode driving sections
20
and
22
in a form of a data stream which is suitable to a gradation processing characteristic of the PDP television. A high voltage generating section
18
produces control pulses, which are needed for driving an PDP by upper and lower address electrode driving sections
20
and
22
, a scan electrode driving section
24
and a sustain electrode driving section
26
, and by combining direct high voltages according to logic levels of control pulses from a timing control section
16
. A power supplying section
30
takes an AC voltage as an input power source and produces all the DC voltages being necessary for the whole PDP system. Upper address electrode driving section
20
applies address pulses to odd address electrode lines of a plasma panel
28
in responsive to high and low levels of red-green-blue (RGB) data provided by data interfacing section
14
c
, and lower address electrode driving section
22
applies address pulses to even address electrode lines of plasma panel
28
in responsive to the high and low levels of the RGB data provided by data interfacing section
14
c
. Being supplied with a DC high voltage from a high voltage generating section
18
, scanning and sustaining sections
24
and
26
provide scanning and sustaining pulses to scanning and sustaining electrode lines of plasma panel
28
, respectively. Timing controlling section
16
is supplied with the vertical and horizontal sync signals from audio/video signal processing section
10
, produces a data reading clock to be supplied to data rearranging section
14
a
, frame memory section
14
b
and data interfacing section
14
c
, and also produces various logic control pulses to be supplied to high voltage driving section
18
.
Generally, for the gradation processing of the PDP, the video data of one field should be rebuilt into multiple subfields and then be rearranged, based on a significance of respective data, in an order from the most significant bit to the least significant bit. Furthermore, prior to being used as a displaying data, the video data in an interlaced scanning way should be converted into a sequential scanning way. Accordingly, frame memory section
14
b
is used as a data storing area for holding the RGB video data of one frame.
Particularly, data interfacing section
14
c
implements cyclic operations of provisionally storing the RGB data of one horizontal line of plasma panel
28
transferred from frame memory
14
b
, rearranging the RGB data to be suitable for an pixel arrangement of plasma panel
28
and providing the rearranged RGB data to upper and lower address electrode driving sections
20
and
22
. In order to rearrange the video data of the whole 480 horizontal lines of plasma panel
28
by a data amount of one horizontal line during an addressing time of one subfield, data interfacing section
14
c
has two provisional data storing sections that each of them can store the data amount of one horizontal line (853×3=2559 bits) supplied from frame memory
14
b
. The reason that data interfacing section
14
c
includes the two provisional data storing sections is to secure a continuity of data. Namely, for a smooth display of a moving picture, data interfacing section
14
c
simultaneously implements an input operation to receive the video data from frame memory
14
b
by using a first provisional data storing section and an output operation to transfer stored video data in a second provisional data storing section to address electrode driving sections
20
and
22
.
In the simultaneous input/output operations of data interfacing section
14
c
, input/output timings of the video data can be characterized as follows. Data interfacing section
14
c
implements only the input (receiving) operation of the video data because the second provisional data storing section does not have a stored video data during a time interval for loading the video data of a first horizontal line among one subfield to the first provisional data storing section. On the contrary, data interfacing section
14
c
implements only the output operation of the video data because no video data is supplied from frame memory
14
b
during a time interval for outputting the video data of a last horizontal line among the subfield to the address electrode driving sections
20
and
22
. Accordingly, during the addressing time of one subfield, one final time that the video data is outputted from data interfacing section
14
c
is behind another final time that the video data is inputted to data interfacing section
14
c
by a delay-time being taken for an input (or output) of the video data of the one horizontal line. The delay-time is about 3 micro-seconds.
Data interfacing section
14
c
implements the input and output operations of the video signal under a control of control signals produced by timing control section
16
. Accordingly, timing control section
16
is requested to produce the control signals suitable for characteristics of input/output operations of the video data of data interfacing section
14
c
as above.
SUMMARY OF THE INVENTION
Therefore, in order to settle the problems of the prior art as described above, it is an object of the present invention to provide a circuit for producing timing control signals to be used for controlling, so that the two provisional data storing sections can simultaneously implement the input and output operations when the data interfacing section which has two provisional data storing sections interfaces the video data from the frame memory to the address electrode driving sections.
In order to achieve the object, there is provided a timing control circuit for a plasma display panel which includes at least a frame memory means, a data interfacing means and an address electrode driving means, comprising:
a first pulse signal generating means for generating a first pulse signal whose level is periodically logic-high with correspondence to a first time interval within which the data interfacing means receives a video data of a whole horizontal line of a plasma panel from the frame memory means;
a second pulse signal generating means for generating a second pulse signal whose level is periodically logic-high with correspondence to a second time interval within which the data interfacing means transfers the video data of the whole horizontal line of the plasma panel to the address electrode driving means;
a third pulse signal generating means for generating a third pulse signal whose level is periodically logic-high with correspondence to a third time interval within which the data interfacing means receives the video data of the whole horizontal line of the pl
Anyaso Uchendu O.
Daewoo Electronics Co. Ltd.
Pillsbury & Winthrop LLP
Saras Steven J.
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