Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-08-06
2001-02-06
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S536000
Reexamination Certificate
active
06184732
ABSTRACT:
FIELD OF THE INVENTION
This invention is generally related to analog electronics and more particularly to differential charge pumps commonly used as part of frequency control circuitry such as a phase locked loop.
BACKGROUND
The differential charge pump is a basic building block of many types of analog circuits, including frequency control circuits such as phase locked loops (PLLs). The PLL accurately controls the frequency and phase of an output oscillatory signal so as to match that of an input oscillatory signal. In this way, the output signal precisely tracks, and essentially duplicates, the input signal. The oscillatory signals may be either digital or analog.
FIG. 4
shows a block diagram of a conventional PLL. The main process in the loop is a charge pump and integrator/filter combination
408
and a voltage controlled oscillator (VCO)
412
. A phase-frequency detector (PFD)
404
provides a differential voltage that is proportional to the phase error. The charge pump and filter
408
condition this error signal to stabilize the PLL loop before sending it to the VCO. The VCO
412
generates an output oscillatory signal whose frequency and phase are proportional to an input differential voltage. An out_phase signal from the VCO
412
is fed back to the PFD
404
and subtracted from an in_phase signal to yield the phase error. Assuming that the control loop can be properly initialized, out_phase should precisely track in_phase in the steady state.
FIG. 5
illustrates the PFD
404
that detects the phase error between two digital signals in_phase and out_phase. The flip-flops and NAND gate in the PFD
404
are configured so that up_sig is asserted high if a rising edge of in_phase leads the corresponding rising edge of the out_phase. On the other hand, if the rising edge of in_phase lags the corresponding rising edge of out_phase, then dn_sig is asserted high. Asserting up_sig indicates that the phase of the oscillatory output signal (see
FIG. 4
momentarily) should be increased, whereas dn_sig indicates that the phase should be decreased. Note that both up_sig and dn_sig are deasserted when the lagging rising edge has been detected. These control signals represent the phase error which is the desired change to be implemented in the oscillatory output signal.
The control signals up_sig and dn_sig are translated into a relatively slow changing differential voltage by the charge pump and filter combination
408
. This differential voltage is then used to control the frequency and phase of the oscillatory output signal through the VCO
412
.
FIG. 6
depicts the charge pump and filter combination
408
in block diagram form. The charge pump
408
includes four current generators
422
. . .
428
. Each one alternatively sources or sinks current from one of a pair of filter and bypass nodes. The current generators are connected to their respective filter/bypass nodes by solid state switches. The switches for current generators
424
and
428
are controlled by up_sig, whereas the switches for current generators
422
and
426
are controlled by dn_sig (see
FIG. 5
momentarily). In typical operation, the voltages on the filter and {overscore (filter)} nodes are subjected to rapid differential corrections: increases in response to up_sig and decreases in response to dn_sig . A loop filter
432
integrates/filters these rapid changes to yield a slow changing differential voltage which is then supplied to the VCO
412
. The bypass and {overscore (bypass)} nodes to help maintain the transistors in the current generators continuously in their saturation region of operation while the generators are not connected to their respective filter nodes, thus providing a differential charge pump circuit whose output voltage in actual operation is more consistent with design values despite manufacturing variations.
The charge pump
408
also includes a common mode control circuit
450
for adjusting the common mode voltage of the filter and {overscore (filter)} nodes to a desired level that is suitable for the VCO
412
. The common mode control circuit
450
includes a set of current generators
462
and
464
that make corrections directly to the filter and filter nodes in response to a difference between desired and actual common mode levels. This approach to controlling the common mode level, however, has the serious drawback of introducing a low impedance path to a power supply node, i.e., ground, through the current generators
462
and
464
, which in turn introduces noise to the filter and {overscore (filter)} nodes and may cause the differential output voltage of the charge pump to drift through charge loss.
SUMMARY
An embodiment of the invention is directed to a circuit including first and second filter nodes for being coupled to a filter and first and second bypass nodes corresponding to the first and second filter nodes, respectively. A charge transfer circuit having at least one charge transfer node is to be alternatively coupled to one of the filter nodes and a corresponding one of the bypass nodes for transferring charge to control a differential voltage of the filter nodes. First and second amplifiers are to buffer the voltages on the first and second filter nodes at first and second outputs which are coupled to the first and second bypass nodes, respectively. The output voltage of each amplifier can be adjusted according to a difference between a control voltage and a common mode voltage of the first and second nodes.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5592120 (1997-01-01), Palmer et al.
patent: 5736880 (1998-04-01), Bruccoleri et al.
patent: 5781048 (1998-07-01), Nakao et al.
patent: 5831484 (1998-11-01), Lukes et al.
patent: 5936455 (1999-08-01), Babanezhad et al.
Fiscus Timothy E.
Johnson Luke A.
Blakely , Sokoloff, Taylor & Zafman LLP
Dinh Paul
Intel Corporation
Wells Kenneth B.
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