Method and apparatus for preventing logic glitches in a 2/n cloc

Details Method and apparatus for preventing logic glitches in a 2/n cloc Method and apparatus for preventing logic glitches in a 2/n cloc

1996-09-06

1998-10-20

Heckler, Thomas M.

G06F 104

Patent

active

058260676

ABSTRACT:
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

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