Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-05-03
2001-11-20
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C716S030000
Reexamination Certificate
active
06321186
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit design, and specifically to verification of design using a logic data structure.
BACKGROUND OF THE INVENTION
Verification of integrated circuit design is a complex activity involving a variety of methods and tools. Design verification is used to eliminate errors prior to the actual manufacture of integrated circuits. By eliminating as many errors as possible prior to manufacturing, the overall cost of implementing a specific integrated circuit design is reduced. Various types of design verification include: simulation techniques, emulation techniques, and formal or static verification techniques.
Simulation techniques include providing test vectors to a simulator to determine whether or not an integrated circuit functions in an expected manner. One problem with using such simulation techniques as a form of design verification is that the amount of time coupled with the number of vectors needed to properly verify a design can be prohibitive. In other words, the number of sequences of vectors needed to thoroughly verify a modern integrated circuit design can run into billions or trillions of vector sequences. To develop this many vector sequences requires a prohibitive amount of time using modem simulation techniques.
Another method of design verification is the physical emulation of the integrated circuit design. Emulation techniques down load circuit definitions into hardware emulators. Generally, these emulators consist of field programmable gate arrays (FPGA's) capable of executing test vectors at speeds several orders of magnitude faster than simulations. However, even using emulation techniques, it is possible for errors to go undetected during design verification. This is the case when test sequences implemented by the emulator are not exhaustive, i.e. they do not create a condition capable of detecting an error.
Yet another form of design verification is the use of a formal verification or static verification check. Formal verification deterministically checks integrated circuit designs based upon predefined conditions or constraints. One such formal verification technique is put forth in the pending U.S. patent application entitled “Method for Performing Model Checking in Integrated Circuit Design” by Matthew J. Kaufmann, et al. filed on Dec. 31, 1997, having application Ser. No. 09/001,751, having a common assignee as the present application, and which is hereby incorporated by reference.
One advantage of using formal verification, is that through formal verification techniques, it is possible to exhaustively perform design verification. In other words, for specified constraints it is possible to exhaustively determine whether or not conditions are met within a current integrated circuit design. However, due to the overhead associated with formal verification techniques, the amount of time and computer memory used to perform formal verification increases exponentially based upon the size of the circuit being checked. In other words, formal verification has a limitation in that for large models or circuits, it is impractical.
Therefore, a new method of performing design verification on large circuit models would be desirable.
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Miller Hillel
Pixley Carl P.
Shultz Stephen Kurt
Yuan Jun
Motorola Inc.
Sergent Douglas W.
Teska Kevin J.
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