Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-08-27
2001-02-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S063000, C365S051000
Reexamination Certificate
active
06188638
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated semiconductor memory having a multiplicity of storage cells as well as a control device for clock-synchronous writing and reading of a data value.
Integrated semiconductor memories with clock-synchronous input and output are known as SDRAMs. Standardization is desirable for a time profile of the signals during the input and output, for example JEDEC, Solid State Technology Division, Council Ballot, JCB-98-46, 20 April 1998, Arlington, Va. According to the standardization proposal, data input and data output signals are coupled to a sampling signal (data strobe signal). The data strobe signal is produced internally to the chip. It is for its part coupled to an externally provided clock which also controls the other functional units of the semiconductor memory. The respective signal profiles for the data output and data input are presented in FIG.
5-1
and FIG. 9.1 of the JEDEC standardization proposal. The data strobe signal is also provided outside the integrated semiconductor memory. It is then available to the modules communicating with the semiconductor memory, in order to control the data interchange during a memory access. This requires a corresponding circuit outlay in the system environment of the semiconductor memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor memory with a control device for clock-synchronous writing and reading that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is universally usable.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory, including:
a multiplicity of storage cells;
a control device for clock-synchronous writing and for reading a data value to and from one of the multiplicity of storage cells, the control device controlling the writing such that the data value represented in a data signal being received by the control device is coupled to a second clock signal and the second clock signal is coupled to a first clock signal received by the control device, the control device controlling the reading such that, in a first operating mode, the data value represented by the data signal is coupled only to the first clock signal, and in a second operating mode the data value represented by the data signal is coupled to the second clock signal and the second clock signal is coupled to the first clock signal; and
a device for producing a control signal to be fed to the control device for switching over between the first operating mode and the second operating mode.
The semiconductor memory according to the invention is operated in the first or the second operating mode during a reading operation. In the first operating mode, the output data signal is coupled only to the system clock that is present in any case and controls the other functional units of the semiconductor memory. In the second operating mode, as in the JEDEC standardization proposal, a further clock signal is provided which is used as a data strobe signal and to which the data output signal is coupled. Since, according to the JEDEC standardization proposal, the coupling between the clock signal, data strobe signal and data signal is tight, that is to say the time tolerance of the relative time reference of the signals with respect to one another is small, the first operating mode without using the data strobe signal is compatible with the second operating mode with use of the data strobe signal. Therefore, the user of the integrated semiconductor memory has a multifunctional semiconductor memory which allows clock-synchronous reading of the semiconductor memory both with and without a data strobe signal.
Refinements of the invention relate to the ways of setting the first and second operating modes. The operating mode can be set using what is referred to as bond options. To do this, a control signal controlling the switching between the first and second operating modes is provided by a bonding pad. The way in which it is bonded defines the signal. A constant voltage, for example a supply voltage, is applied to the pad in order to set one operating mode. To do this, a bonding wire is bonded from the pad to a lead finger which is at a supply potential. The lead finger is conventionally also bonded to a further supply potential pad. For the other operating mode, the pad remains unconnected, the control signal being produced internally to the circuit by pull-up or pull-down elements.
As an alternative to the bond option, the control signal may be set by a mode register. A register of this type is in any case present on the integrated semiconductor chip for setting other operating parameters. The control signal is tapped at the output of a memory element of the mode register. The memory element is set to the desired status during a phase of initializing the semiconductor chip. This status is externally delivered to the mode register, for example by a microcontroller controlling the system.
Although the semiconductor memory can be operated in various operating modes during reading, only a single circuit configuration is necessary. By simple methods such as the bond option or setting the mode register, the operating mode is tailored to the system environment in question.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory with a control device for clock-synchronous writing and reading, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5572479 (1996-11-01), Satou
patent: 5629903 (1997-05-01), Agata
patent: 54-123841 (1979-09-01), None
“A 2.5-ns Clock Access, 250-MHz, 256 Mb SDRAM with Synchronous Mirror Delay”, Takanori Saeki et al., IEEE Journal of Solid-State Circuit, vol. 31, No. 11, Nov. 1996, pp. 1656-1668.
JEDEC, Solid State Technology Division, Council Ballot, JCB-98-46, Apr. 20, 1998, Arlington, Virginia, pp. 1-16.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Tran Andrew Q.
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