Buffer circuit

Details Buffer circuit Buffer circuit

1999-11-24

2001-05-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S362000, C327S484000, C327S491000

Reexamination Certificate

active

06225839

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a buffer circuit having high input impedance.
BACKGROUND OF THE INVENTION
For a buffer circuit utilizing bipolar transistor, a leakage current deriving from the transistor base current is generated at the signal input terminal, such that the input impedance of the buffer circuit is lowered. In order to counter this, effect usually a current compensation current is provided to compensate the base current of the transistor.
FIG. 3
shows an example of a buffer circuit having a current compensation circuit. As shown in the figure, in addition to a transistor Q
11
that constitutes an emitter follower, this buffer circuit is provided with a current compensation generation circuit comprising transistor Q
12
and transistors Q
13
and Q
14
. Transistors Q
11
and Q
12
are npn transistors, and transistors Q
13
and Q
14
are pnp transistors.
The base of transistor Q
11
is connected to the input terminal of the buffer circuit. The emitter of transistor Q
11
is connected to current source IS
10
, and is connected to the output terminal of the buffer circuit. The emitter of transistor Q
12
is connected to the collector of transistor Q
11
, and the collector is connected to power source voltage V
CC
. Transistors Q
13
and Q
14
constitute a current mirror circuit. The bases of transistors Q
13
and Q
14
are connected to each other, and that connection is connected to the collector of transistor Q
14
as well as to the base of transistor Q
12
. The emitters of transistors Q
13
and Q
14
are connected to power source voltage V
CC
, and the collector of transistor Q
13
is connected to the base of transistor Q
11
, in other words, to the signal input terminal.
When an input signal V
IN
is input to the input terminal of the buffer circuit, a signal V
OUT
is output from the emitter of transistor Q
11
, in other words, from the output terminal of the buffer circuit, in response to the input signal V
IN
. When the current value of current source IS
10
is made equal to I
1
, the emitter current of transistor Q
11
becomes I
1
. Furthermore, when the base current of transistor Q
11
is made equal to I
B1
, the emitter current I
2
of transistor Q
12
—in other words, of the collector of transistor Q
11
—is found using the following formula:
Formula 1
I
2
=I
1
−I
B1
  (1)
Since the base current I
B1
is extremely small, virtually the same current flows in the emitter of transistor Q
12
as in the emitter of transistor Q
11
. By means of the current mirror circuit formed by transistors Q
13
and Q
14
, a current I
3
that is virtually the same as the base current I
B2
of transistor Q
12
is output to the collector of transistor Q
13
. The current I
3
is input to the base of transistor Q
11
as a compensation current. Consequently, The current I
IN
flowing into the input terminal becomes the difference current between the base current I
B1
of transistor Q
11
and the current I
3
generated by the current mirror. It is calculated using the following formula:
Formula 2
I
IN
=I
B1
=I
3
  (2)
As can be seen from Formula 2, the base current of transistor Q
11
is partially offset by means of the compensation current generated by the current compensation circuit, such that the input current of the input terminal is decreased and a high input impedance is attained for the buffer circuit.
However, with the aforementioned conventional buffer circuit, when the current amplification ratio of the pnp transistors Q
13
and Q
14
which form the current compensation circuit is small, the compensation current I
3
that is generated cannot completely compensate the base current I
B1
of transistor Q
11
. Furthermore, there is a disadvantage in that the input dynamic range of the buffer circuit is reduced by the voltage V
BEP
between the bases-emitters of the pnp transistors Q
13
and Q
14
.
For example, when the current amplification ratio of the npn transistors Q
11
and Q
12
is made &bgr;
N
and the current amplification ratio of the pnp transistors Q
13
and Q
14
is made &bgr;
P
, the base current I
B1
of transistor Q
11
becomes I
1
/(1=&bgr;
N
) and the emitter current I
2
of transistor Q
12
becomes &bgr;
N
I
1
/(1+&bgr;
N
), the same as that of the collector current of transistor Q
11
. Therefore, the base current I
B2
of transistor Q
12
is found with the following formula.
Formula 3
I
B2
=I
2
/(
I+&bgr;
N
)=&bgr;
N
I
1
/(1+&bgr;
N
)
2
  (3)
Furthermore, for the aforementioned current mirror circuit, the following relationship is established for the collector current I
3
of transistor Q
13
and the base current I
B2
of transistor Q
12
.
Formula 4
I
B2
=I
3
+2
I
3
/&bgr;
P
=(2+&bgr;
P
)
I
3
/&bgr;
P
From Formulas 3 and 4, the following formula can be found.
Formula 5
I
3
=&bgr;
N
&bgr;
P
I
1
/(1+&bgr;
N
)
2
(2+&bgr;
P
)  (5)
Consequently, the input current I
IN
of Formula 2 is found in the following manner.
Formula 6
I
IN
=I
B1
−I
3
=I
1
/(1+&bgr;
N
)−&bgr;
N
&bgr;
P
I
1
/(1+&bgr;
N
)
2
(2+&bgr;
P
)=[2(1+&bgr;
N
)+&bgr;
P
]I
1
/(1+&bgr;
N
)
2
(2+&bgr;
P
)  (6)
&bgr;
N
satisfies [the inequality] (&bgr;
N
>>1); in addition, when &bgr;
P
is extremely small compared to &bgr;
N
, from Formula 6 the input current I
IN
is found with the following approximation method.
Formula 7
I
IN
=2/&bgr;
N
(2+&bgr;
P
  (7)
From Formulas 6 and 7, when the current amplification ratio &bgr;
P
of pnp transistors Q
13
and Q
14
which form the current compensation circuit is small, the base current of transistor Q
11
cannot be compensated sufficiently by means of compensation current I
3
, such that the input current I
IN
cannot be reduced sufficiently and the input impedance of the buffer circuit is reduced.
The present invention was devised due to said circumstances, and its purpose is to offer a buffer circuit that is able to achieve a lowering of the input leakage current and to achieve a high input impedance by compensating the base current of the transistor by means of a current compensation circuit; and that is able to avoid a lowering of the input dynamic range by means of the current compensation circuit.
SUMMARY OF INVENTION
In order to achieve the aforementioned purposes, the buffer circuit of the present invention has: a signal output transistor whose base is connected to a signal input terminal, whose collector is connected to a first power source voltage, and whose emitter is connected to a signal output terminal; first and second transistors whose respective emitters are connected to each other, constituting a differential circuit; a voltage-setting transistor whose collector is connected to a first voltage source and whose emitter is connected to the base of the aforementioned first transistor;
a reference voltage source that supplies a reference voltage to the base of the aforementioned second transistor;
a compensation current generation transistor whose emitter is connected to the first power source voltage, and whose collector is connected to the base of the aforementioned voltage-setting transistor;
and a compensation current supply transistor whose emitter is connected to the first power source voltage, and whose collector is connected to the base of the aforementioned signal output transistor;
and the base of the aforementioned compensation current supply transistor and the base of the compensation current generation transistor are connected to the collector of the aforementioned second transistor.
In addition, with the present invention, ideally a first current source is connected between the emitter of the aforementioned signal output transistor and a second power source voltage, a second current source, is connected between the emitter of the aforementioned voltage-setting transistor and second power source voltage, a third current source is connected between

Affiliated with

Also associated with

Rating

Buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2568961