ATM cell transmission system

Details ATM cell transmission system ATM cell transmission system

1998-12-11

2001-10-23

Olms, Douglas (Department: 2732)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S419000

Reexamination Certificate

active

06307858

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an ATM (Asynchronous Transfer Mode) cell transmission system having an ATM layer device and more than one PHY (physical) layer devices connected to the ATM layer device by way of a data path interface according to Utopia (Universal Test & Operations PHY interface for ATM) Level 2 specification for transmitting ATM cells through the PHY layer devices.
Specifications of interface between the ATM layer and the physical layer for absorbing diversity of PHY layer devices are studied in The ATM Forum as the Utopia.
A data path interface defined for interfacing one ATM layer device with one PHY layer device is the Utopia Level 1 interface, and that defined for interfacing one ATM layer device with more than one PHY layer devices is the Utopia Level 2 interface, which is described in “Utopia, An ATM-PHY Interface Specification”, pp. 1 to 66, Utopia Level 2, v1.0 (af-phy-0039.000), published by The ATM Forum Technical Committee.
FIG. 15
is a block diagram illustrating a basic configuration of an ATM cell transmission system having an ATM layer device
1
, a plurality of PHY layer devices
2
-
0
to
2
-M and a data path interface
3
according to the Utopia Level 2 for interfacing the ATM layer device
1
with the PHY layer devices
2
-
0
to
2
-M for transmitting ATM cells through the PHY layer devices
2
-
0
to
2
-M. Addresses O to M are assigned to the PHY layer devices
2
-
0
to
2
-M, respectively.
FIG. 16
is a timing chart for illustrating operation of the data path interface
3
, which is described in page 19 of the “Utopia, An ATM-PHY Interface Specification”.
In
FIGS. 15 and 16
, TxClk denotes a transmission clock having a clock cycle T, which is delivered from the ATM layer device
1
to each of the PHY layer devices
2
-
0
to
2
-M. TxAddr denotes an address signal whereby addresses of the PHY layer devices
2
-
0
to
2
-M are transmitted from the ATM layer device
1
to the PHY layer devices
2
-
0
to
2
-M for polling and selecting one of the PHY layer devices
2
-
0
to
2
-M. Each of the addresses is represented with five-bit data and an address ‘11111’ (‘1F’ in hexadecimal) represents a null PHY port assigned to neither of the PHY layer devices
2
-
0
to
2
-M.
TxClav (Transmission Cell Available) denotes a cell transmission allowance signal having three statuses transmitted from one of the PHY layer devices
2
-
0
to
2
-M to the ATM layer device
1
. When a PHY layer device is polled with its address transmitted by the address signal TxAddr at a clock cycle, the designated PHY layer device makes HIGH the cell transmission allowance signal TxClav for next one clock cycle on condition that the PHY layer device can accept one more ATM cell as a whole, and makes LOW the cell transmission allowance signal TxClav for a period of the next one clock when the PHY layer device cannot accept the whole ATM cell, as shown in
FIG. 16
, wherein the cell transmission allowance signal TxClav is made HIGH by the PHY layer devices
2
-(N−3),
2
-(N+3) and
2
-N having addresses N−3, N+3 and N, respectively, at clock cycles #4, #10 and #14, polled at clock cycles #3, #9 and #13, respectively, and made LOW by the PHY layer devices
2
-(N+2),
2
-(N−2),
2
-(N−1),
2
-(N+1) and again by the PHY layer device
2
-(N+1).
An ATM cell consists of a cell header of 5 octets (bytes) H
1
to H
5
and a payload of 48 octets P
1
to P
48
, whereof a part P
35
to P
48
of an ATM cell and H
1
to H
5
of another ATM cell is depicted in
FIG. 16
as transmission data TxData. The PHY layer device polled with its address determines to make HIGH or LOW the cell transmission allowance signal TxClav according to whether the PHY layer device has a room or not for receiving the 53-octet data H
1
to H
5
and P
1
to P
48
of the ATM cell as a whole.
TxEnb (Transmission Enable). denotes a transmission enabling signal delivered from the ATM layer device
1
to the PHY layer devices
2
-
0
to
2
-M for notifying transmission of cell data, indicating a selected PHY layer device whereto the cell data is to be forwarded by putting address thereof on the address signal TxAddr at the same clock cycle.
TxData (Transmission Data) denotes cell data delivered from the ATM layer device
1
to the selected PHY layer device, wherein cell header of five octets H1 to H5 followed by payload of 48 octets P
1
to P
48
are transmitted octet by octet in synchronization with the transmission clock TxClk, and TxSOC (Transmission Start Of Cell) denotes a transmission start signal indicating beginning of the cell data, that is, a first header octet H1 of an ATM cell to be transmitted.
As above described, the ATM layer device
1
polls status of each one of the PHY layer devices
2
-
0
to
2
-M by putting its address on the address signal TxAddr one by one, and a PHY layer device designated by a polling address at a clock cycle drives the cell transmission allowance signal TxClav to HIGH or LOW for a period of one clock cycle just following the clock cycle of the polling address. Then, selecting an appropriate PHY layer device among PHY layer devices which have made HIGH the cell transmission allowance signal TxClav, the ATM layer device
1
notifies the selection by asserting the transmission enabling signal TxEnb for a clock cycle and putting address of the selected PHY layer device on the address signal TxAddr at the same time. When the transmission enabling signal TxEnb is made HIGH, every of the PHY layer devices
2
-
0
to
2
-M checks the address on the address signal TxAddr, and the selected PHY layer device acknowledges the selection by driving the cell transmission allowance signal TxClav to HIGH at the next clock cycle. The selection remains valid until the transmission enabling signal TxEnb is again made HIGH.
In the example of
FIG. 16
, payload octets P
35
to P
48
are transmitted to a selected PHY layer device
2
-N at clock cycles #1 to #14 as the transmission data TxData, which represents a part of a cell transmission cycle consisting of 54 clock cycles, that is, 53 clock cycles to #14 for transmitting five header octets H
1
to H
5
, 48 payload octets P
1
to P
48
, and one clock cycle #15 for designating a next selection.
For preparing the next selection, polling of the PHY layer devices
2
-
0
to
2
-M is performed in parallel with the data transmission during second to 53-th clock cycles of a cell transmission cycle, as shown in
FIG. 16
, wherein polling for selecting the PHY layer device
2
-(N+3) is performed until clock cycle #14 where the last payload octet P
48
is transmitted, and polling for selecting a next PHY layer device begins at clock cycle #17 where the second header octet H
2
is transmitted.
In the example, the cell transmission allowance signal TxClav indicates that the PHY layer devices
2
-(N−3),
2
-(N+3) and
2
-N having respective addresses N−3, N+3 and N can accept data of an ATM cell as a whole. The PHY layer device
2
-N, which is under receiving cell data at the cell transmission cycle, drives the cell transmission allowance signal TxClav to HIGH on condition that it can accept another whole ATM cell besides cell data actually receiving.
In the following paragraphs, PHY layer devices which drives the cell transmission allowance signal TxClav to HIGH when it can accept a whole ATM cell besides cell data actually receiving, if there is any, are to be called the normal PHY layer devices according to a normal specification defined in the Utopia Level 2 specification.
Returning to the example of
FIG. 16
, selecting the PHY layer device
2
-(N+3) among the above PHY layer devices
2
-(N−3),
2
-(N+3) and
2
-N, the ATM layer device
1
notifies the selection by putting the address N+3 on the address signal TxAddr at clock cycle #15, and begins to transmit cell data of a next ATM cell at clock cycle #16 from a top octet, namely, the first header octet H
1
as the tr

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