Multi-input comparator

Details Multi-input comparator Multi-input comparator

1998-09-29

2001-02-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S058000, C327S200000, C327S067000

Reexamination Certificate

active

06191623

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic circuits, and more particularly to comparator circuits which can support two or more inputs.
BACKGROUND OF THE INVENTION
Conventional comparators generally determine which of two inputs is the greater or the lesser of the two. An example of such a comparator is a sense amplifier typically used in applications such as dynamic random access memory (DRAM) cells.
FIG. 1
shows a schematic diagram of a conventional sense amplifier
10
implemented using metal-oxide-semiconductor (MOS) field effect transistors. When the clock signal CK applied to sense amplifier
10
is at a logic low level, transistors MP
1
and MN
1
are off while transistor MPA is enabled. This equalizes the voltages at nodes A and B. At this time, a voltage difference can be introduced between A and B, since the resistance of MPA is very high. For example, the voltage at node A can be set higher than the voltage at node B by appropriate application of signal voltages to corresponding inputs IN
A
and IN
B
, respectively. The clock signal CK is then permitted to go to a logic high level, such that transistors MP
1
and MN
1
are turned on, and transistor MPA is turned off. This activates the random access memory (RAM) cell made up of transistors MP
2
, MP
3
, MN
2
and MN
3
. Since the voltage at node A was set to be higher than the voltage at node B, positive feedback through the cell transistors will cause node A to approach the supply voltage V
DD
, while node B will approach the supply voltage V
ss
, which may be ground potential. As a result, the initial difference established between the voltages at nodes A and B, which may have been on the order of several millivolts, can be amplified significantly.
Unfortunately, using conventional two-input comparators configured as shown in
FIG. 1
to determine, for example, which of three inputs is greater or lesser than the others, generally requires comparisons of each pair of inputs and then further comparisons of the previous comparison results. Multi-input comparators configured in this manner can also exhibit excessive computation time and signal delay, in that each stage of comparison generally requires a separate cycle of the clock signal. Furthermore, such arrangements can require an unduly large amount of circuit area, and consume an excessive amount of power. A need therefore exists for an improved multi-input comparator which is more computationally efficient, requires less circuit area, and consumes less power than conventional multi-input comparators.
SUMMARY OF THE INVENTION
A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of input signal values. In an illustrative embodiment, a multiinput comparator is configured using two or more interconnected inversion circuits, with each of the inversion circuits having an input node associated therewith. The input node of each of the inversion circuits is coupled to an output of at least one of the other inversion circuits. As a result of this feedback arrangement, after activation of the inversion circuits, the voltages at the input nodes are indicative of the relative magnitude of the signal values previously applied thereto.
In accordance with another aspect of the invention, the inversion circuits in the comparator may be constructed using, for example, single-inverter or multiple-inverter building blocks. A multiinput comparator with two inputs, three inputs, or more than three inputs can be constructed by replicating the corresponding single-inverter or multiple-inverter blocks. For example, one or more of the inversion circuits may be characterized as a two-inverter circuit with one output and more than one input, or as a two-inverter circuit with one input and more than one output. As another example, one or more of the inversion circuits may be characterized as a combination of two single-inverter circuits in which each of the inverters has one output and more than one input, or as a combination of two single-inverter circuits in which each of the inverters has one input and more than one output.
Advantageously, a multi-input comparator configured in accordance with the invention is more computationally efficient, requires less circuit area, and consumes less power than a conventional multi-input comparator. A comparator in accordance with the invention can be configured to include two or more inputs, and can be constructed in a straightforward manner by replicating inverter-based building blocks. These and other features and advantages of the present invention will become more apparent from the accompanying drawings and the following detailed description.


REFERENCES:
patent: 4149160 (1979-04-01), Bozarth et al.
patent: 4962341 (1990-10-01), Schoeff
patent: 5381054 (1995-01-01), Standley
patent: 5400007 (1995-03-01), McClure
patent: 5818267 (1998-10-01), Fujio et al.
S. Aur et al., “Identification of DRAM Sense-Amplifier Imbalance Using Hot Carrier Evaluation,” IEEE Journal of Solid-State Circuits, vol. 27, No. 3, pp. 451-453, Mar. 1992.

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