Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-12-23
2001-05-01
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S750000
Reexamination Certificate
active
06225678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of capacitors on semiconductor devices. Specifically this invention identifies a new layout technique for fabricating an array of matched capacitors on semiconductor devices using a continuous top electrode.
2. Description of the Related Art
The matching of capacitors is defined as the relative size and capacitance (in farads) of the capacitors in the array with respect to each other. Matching also requires that parasitic effects, i.e. cross-talk between capacitors and fringe capacitance, i.e. capacitance beyond the interface of the electrodes, be minimized. In the alternative, matching may be accomplished by providing for equal distribution of the parasitics amongst the array. There are many integrated circuit applications that require a capacitor array that is accurately matched. One such application is for use with a Successive Approximation Register in an Analog to Digital Converter, shown in
FIG. 1
as a simple 4-bit register, capacitor array and comparator.
As shown in
FIG. 2
, which is a cross section of a typical capacitor array layout under the prior art, each top conductive electrode corresponds to a bottom conductive electrode. The parasitic capacitance components as between the top and bottom electrodes and the substrate may be significant. Also significant are the crosstalk effects as between adjacent capacitors and fringe capacitance which occurs beyond the active area of the capacitor electrodes.
In the prior art, excessive silicon area is required by the alignment and process rules of fabricating a capacitor array where both the top and bottom electrodes are unit cells. Also, increasing the spacing between the individual conductive electrode pairs can serve to offset the deleterious effects of parasitic and crosstalk capacitance. However, the additional spacing requires a larger silicon area which then exposes the array to greater process variations. This may lead to even greater difficulty in matching the array.
Another problem in creating a matched capacitor array is that the last row or column of capacitors will function differently because it is bordered only on one side by other unit capacitors. Typical prior art capacitor arrays solve this problem by surrounding the periphery of the array with “dummy” or unused rows of unit capacitors. The dummy rows are used to address process sensitivities, by surrounding each capacitor with similar features to assist in uniform etching. In the prior art, both the bottom and top electrodes of the dummy capacitor rows are grounded, i.e. not connected to the active array.
However, even with such prior art techniques as described above, significant parasitic and crosstalk capacitance remains as well as non-efficient use of semiconductor “real estate” or area. Thus, a need exists to provide for an improved layout of capacitors on an integrated circuit where the matching of the capacitors and the use of the silicon area are optimized
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved layout technique for a capacitor array on an integrated circuit.
It is another object of the present invention to provide and improved layout technique for a capacitor array on an integrated circuit where the matching of capacitors is optimized.
It is another object of the present invention to provide an improved layout technique for a capacitor array on an integrated circuit where rather than minimizing the parasitic and fringe capacitances of the unit cells in the array, the parasitic and fringe capacitances are incorporated into the total capacitance of each of the unit cells in the array and the parasitic and fringe capacitances of each unit cell are designed to be approximately equal.
It is another object of the present invention to provide an improved layout technique for a capacitor array on an integrated circuit which optimizes the use of semiconductor area.
It is another object of the present invention to provide an improved layout technique for a capacitor array on an integrated circuit which minimizes the number of masks required for fabrication.
It is another object of the present invention to provide an improved layout technique for a capacitor array on an integrated circuit which matches the parasitic and fringe capacitances as between unit capacitors.
In accordance with one embodiment of the present invention, a matching capacitor array comprises a plurality of bottom electrodes arranged in a matrix of N rows and M columns, a dielectric layer coupled to the plurality of bottom electrodes, and a plurality of top electrodes arranged as M columns coupled to the dielectric layer. Each of the plurality of top electrode columns coincides with the plurality of bottom electrode M columns. Each of the plurality of top electrode columns spans the N rows of the plurality of bottom electrodes. The matching capacitor array is implemented on a single, monolithic integrated circuit.
The matching capacitor array is comprised of matching capacitor unit cells, each cell may be seen to comprise a bottom electrode; a dielectric material coupled to the bottom electrode; a portion of a continuous top electrode coupled to the dielectric layer wherein the continuous top electrode spans a plurality of the bottom electrodes where each of the bottom electrodes are geometrically and electrically identical. The matching capacitor unit cell is implemented on a single, monolithic integrated circuit.
REFERENCES:
patent: 5140327 (1992-08-01), Bruce et al.
L. M. Arzubi et al., “Metal-Oxide Semiconductor Capacitor,” IBM Technical Disclosure Bulletin, vol. 17, No. 6 (Nov. 1974) pp. 1569-1570.
Wojewoda Igor
Yach Randy L.
Baker & Botts L.L.P.
Crane Sara
Microchip Technology Incorporated
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