Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1998-07-09
2001-02-13
Le, Amanda T. (Department: 2734)
Pulse or digital communications
Equalizers
Automatic
C375S235000, C375S350000, C708S301000, C708S316000, C708S319000
Reexamination Certificate
active
06188723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a finite impulse response (FIR) filter for wave-shaping digital quadrature amplitude modulation (QPM) symbols, in which multipliers are replaced with multiplexers, the replaced multiplexers are utilized to receive the symbols directly from a symbol encoder without zero (0) interpolations, and the critical path is reduced by shifting the positions of delay devices.
2. Description of the prior art
Generally, in the digital 2
k
QAM method, successive k binary data are encoded into pairs of in-phase quadrature symbols, and are transmitted after wave-shaping, thereby reducing the transmission band into 1/k through the channel.
FIG. 1
is a circuit diagram showing the constitution of the general FIR filter.
The general FIR filter is a wave-shaping FIR filter of a 32-tab digital QAM transmitting section which satisfies the digital QAM 51,84 Mbps downstream transmission standard using symbol values of 1 and 3 of Class B which is recommended in DAVIC 1.2 spec. part 8.
The general FIR filter includes
31
modules (
10
−n) and a multiplier
104
. Each of the modules
10
−n includes a D flip flop, a multiplier and an adder. Therefore, the general FIR includes
32
multipliers,
31
adders and
31
D flip flops.
The multiplier
104
internally has a pre-set filter tab coefficient ho, and thus, the inputted symbol value is multiplied by the pre-set filter tab coefficient ho to supply the product to an adder
103
of a first module
10
-
1
.
In the first module
10
-
1
, a D flip flop
101
is used as a delay means to carry out a temporarily storing function. Further, it receives symbol values and clock signals through its input terminal to output one of the inputted symbols through an output terminal. A multiplier
102
multiplies one of the output symbols of the D flip flop
101
by the pre-set filter tab coefficient hl. An adder
103
sums up the output values of the multipliers
102
and
104
to supply the summed value to an adder
103
-
1
of a second module
10
-
2
.
In the second module
10
-
2
having the same constitution as that of the first module
10
-
1
, a D flip flop
101
-
1
serves as a delay device to receive clock signals and the output values of the D flip flop
101
of the first module
10
-
1
through its input terminal so as to output symbol values through its output terminal. A multiplier
102
-
1
multiplies one of the output symbol values of the D flip flop
10
l-
1
by a pre-set filter tab coefficient H
2
. An adder
103
-
1
sums up the output value of the multiplier
103
-
1
and the summed value of the adder
103
of the first module
10
-
1
to supply the summed value to an adder (not illustrated) of a third module (not illustrated).
The third to
31
st modules have the same constitution as that of the second module
10
-
2
, and carry out the same operations as that of the second module
10
-
2
. In the
31
st module
10
-
31
, the final output values are obtained by multiplying the output symbol value of the D flip flop
101
-
30
by a filter tab coefficient h
31
and by summing the summed value of the preceding adder (not illustrated) and the summed value of the adder
103
-
30
.
Now the general FIR filter will be described as to its operations.
The input symbol (x[2:0]) is one of four numbers −3, −1, 1 and 3. One bit among the three bits is used as the code bit of the symbol, while the remaining two are used as the magnitude bits of the symbol.
In the case where the wave shaping filter consists of the general FIR, the FIR filter receives clock signals at a speed of 51.84 Mbps by interpolating three zeros (0) between the respective symbols to solve the problem of the mismatching between the output operating speed (12.96 Mbps) of a symbol encoder (not illustrated) and the input speed (51.84 Mbps) of the wave-shaping filter.
The critical path which represents the longest path from the delay device to the output stage for obtaining one signal requires one multiplier and 31 adders.
Therefore, the conventional general FIR filter has a complicated structure due to the multipliers and adders. Further, due to the difference between the output speed of the symbol encoder and the operating speed of the wave-shaping FIR filter, zeros (0) should be inserted into between the symbols so as to prevent the mixing of the data. Further, in order to obtain one output, a long critical path has to be gone through, with the result that a long time period is consumed in obtaining one output value.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above described disadvantages of the conventional technique.
Therefore it is an object of the present invention to provide a FIR filter in which multipliers are replaced with multiplexers, the replaced multiplexers are utilized to receive the symbols directly from a symbol encoder without zero (0) interpolations, and the critical path is reduced by shifting the positions of delay devices.
In achieving the above object, the FIR filter according to the present invention includes: a first multiplexing means for receiving input symbol data as selection signals to select one value from among products obtained by multiplying symbol values by a pre-set filter tab coefficient; a first FIR means for delaying the externally inputted symbol data, and for utilizing the delayed symbol data as selection signals to sum up the selected multiplication product (selected from among products obtained by multiplying symbol values by a pre-set filter tab coefficient) and the selected value selected by the first multiplexing means; and a second FIR means for delaying again the delayed symbol data of the first FIR means, and for utilizing the delayed symbol data as selection signals to sum up the selected multiplication product and the output value of the first FIR means.
In another aspect of the present invention, the FIR filter according to the present invention includes: a first FIR means for circulatively outputting products obtained by multiplying respective symbol values by filter tab coefficients in accordance with count signals (the multiplications being carried out in accordance with the sequence of the inputted symbol data), to match an input operation speed to an output operating speed during a symbol period even without insertions of zeros (0); a second FIR means for delaying the externally inputted symbol data to sum up the circulatively outputted values of products obtained by multiplying symbol values by filter tab coefficients in accordance with the count signals (the multiplications being carried out in accordance with the sequence of the inputted symbol data) and the output values of the first FIR means, based on the delayed symbol data; and a third FIR means for summing up the circulatively outputted values of products outputted in accordance with the count signals and obtained by multiplying symbol values (delayed by the second FIR means) by filter tab coefficients, and the output values of the second FIR means.
In still another aspect of the present invention, the FIR filter according to the present invention includes: a first FIR means for circulatively outputting products obtained by multiplying respective symbol values by filter tab coefficients in accordance with count signals (the multiplications being carried out in accordance with the sequence of the inputted symbol data), to match an input operation speed to an output operating speed during a symbol period even without insertions of zeros (0); and at least one second FIR means for sequentially storing the output values of the first FIR means, to sum up the sequentially outputted values and the circulatively outputted values of the products obtained by multiplying the symbol values by filter tab coefficients in accordance with the externally inputted symbol data, the circulative outputting being done in accordance with the count signals, whereby a critical path is reduced.
REFERENCES:
patent: 5479363 (1995-12-01), Willson, Jr. et al.
pa
Choi Min Ho
Kim Bong Tae
Kim Hyup Jong
Lee Jeong Jin
Electronics and Telecommunications Research Institute
Jacobson Price Holman & Stern PLLC
Le Amanda T.
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