Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-11-08
2001-10-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000
Reexamination Certificate
active
06310821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock-synchronous semiconductor memory device and access method thereof which operates synchronously with a basic clock signal, and, in particular, to a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set synchronously with a basic clock signal, and a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set when a high-frequency basic clock signal is used.
2. Description of the Prior Art
The inventors of the present invention have previously proposed a basic method for controlling a memory operation for a semiconductor memory device synchronized with a basic clock signal (Japan Application No. 3-255354).
At that time, several methods were illustrated for controlling a memory access by means of an external control signal, but nothing was disclosed how to set a external control signals synchronously with a basic clock signal and with respect to setting specific timing for an address signal or the like for the external control signals.
Moreover, there is a problem that it is difficult to access data when a high-frequency basic clock signal is used in a conventional a clock-synchronous semiconductor memory device and access method thereof.
SUMMARY OF THE INVENTION
An object of the present invention, with due consideration to the drawbacks of such conventional semiconductor memory device and method thereof, to provide a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set by external control signals synchronously with an external basic clock signal.
A further object of the present invention is to provide a clock-synchronous semiconductor memory device and a method thereof for access of a clock-synchronous semiconductor memory device wherein an address for access is easily set for the cases where the basic system cycle is short and where the basic system cycle is long.
A further object of the present invention is to provide a clock-synchronous semiconductor memory device which is capable of switching internal operation to conform to the length of the basic incorporated system cycle.
In accordance with one preferred embodiment, there is a method for accessing a clock-synchronous semiconductor memory device, used for access of data, synchronized with a continuous, external clock signal, comprising the steps of:
setting an initial address for data access of the clock-synchronous semiconductor memory device from the cycle of the clock signal for which a control signal from at least more than one type of clock signal, other than the clock signal, supplied to the semiconductor memory device is maintained at a specified level;
counting output of data from the set initial address after the initial address is set; and
starting from a specified cycle in the cycles of the clock signal.
In accordance with another preferred embodiment, there is a method for accessing a clock-synchronous semiconductor memory device used for access of data, synchronized with a continuous, external clock signal, comprising the steps of:
setting an initial address for data access of the clock-synchronous semiconductor memory device from conditions under which a first control signal from at least more than one type of clock signal, other than the clock signal, supplied to the semiconductor memory device is maintained at a specified level; and
starting the output of data from the set initial address from a specified cycle number of the clock signal, counting from after a second control signal supplied to the semiconductor memory device has been maintained at a specified level.
In accordance with another preferred embodiment, there is a method for accessing a clock-synchronous semiconductor memory device by which access of data is possible, synchronized with a continuous, external clock signal, comprising the steps of:
setting an initial address for data access of the clock-synchronous semiconductor memory device from conditions under which a first control signal from at least more than one type of clock signal, other than the clock signal, supplied to the semiconductor-memory device is maintained at a specified level; and
selecting the output of data from the set initial address by either one of two types ((A) or (B)) of access methods by means of external control provided to the semiconductor memory device prior to setting the initial address for the data access by means of the first control signal;
wherein: (A) is an access method by which the output of data from the set initial address is started immediately after the setting of the initial address; and
(B) is an access method by which the output of data from the set initial address is synchronized with a clock signal and is started from a specified cycle number of clock signals, counting after a second control signal supplied to the semiconductor memory device has been maintained at a specified level.
In accordance with another preferred embodiment, there is a method for accessing a clock-synchronous semiconductor memory device with which access of data is possible, synchronized with a continuous, external clock signal, comprising the steps of:
setting an initial address for data access of the clock-synchronous semiconductor memory device from conditions under which a first control signal from at least more than one type of clock signal, other than the clock signal, supplied to the semiconductor memory device is maintained at a specified level; and
selecting the output of data from the set initial address by either one of two types ((A) or (B)) of access methods by means of external control provided to the semiconductor memory device prior to setting the initial address for the data access by means of the first control signal;
wherein: (A) is an access method by which the output of data from the set initial address is started directly after the setting of the initial address; and
(B) is an access method by which the output of data from the set initial address is synchronized with a clock signal and is started from a specified cycle number of clock signals, counting after the initial address has been set.
In accordance with another preferred embodiment, there is a clock-synchronous semiconductor memory device comprising:
memory means comprising a plurality of memory cells arranged in rows and columns;
count means for counting the actual number of cycles of a continuous, externally-supplied basic clock signal;
control means for inputting at least more than one type of externally-supplied control signal other than the basic clock signal. for which the control signal is at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory means; and
data input/output means for executing a data access operation for the address set by the control means;
wherein: the output of data from the memory means through the data input/output means is started after the setting of the initial address by the control means, and after a specified number of basic clock signals has been counted by the count means.
In accordance with another preferred embodiment, there is a clock-synchronous semiconductor memory device comprising:
memory means comprising a plurality of memory cells arranged in rows and columns;
count means for counting the actual number of cycles of a continuous, externally-supplied basic clock signal;
control means for inputting at least more than one type of externally-supplied control signal, other than the basic clock signal, for which a first control signal is at a specified level, and for setting the initial address for data access of the memory means; and
data input/output means for executing a data access operation for the address set by the control means;
wherein: the output of data from the memory means through the data input/output means is started after the setting of a second. control signal of the externally-provided contr
Kuyama Hitoshi
Toda Haruki
Foley & Lardner
Kabushiki Kaisha Toshiba
Le Vu A.
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