Computer graphics processing and selective visual display system – Display driving control circuitry – Intensity or color driving control
Reexamination Certificate
2000-01-18
2001-12-04
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Intensity or color driving control
C345S692000
Reexamination Certificate
active
06326980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electronic driver circuits, and more particularly to a novel circuit and method for using compound data words to drive a display.
2. Description of the Background Art
FIG. 1
shows a single pixel cell
100
of a typical liquid crystal display. Pixel cell
100
includes a liquid crystal layer
102
, contained between a transparent common electrode
104
and a pixel storage electrode
106
, and a storage element
108
. Storage element
108
includes complementary data input terminals
110
and
112
, data output terminal
114
, and a control terminal
116
. Responsive to a write signal on control terminal
116
, storage element
108
reads complementary data signals asserted on a pair of bit lines (B+ and B−)
118
and
120
, and latches the signal on output terminal
114
and coupled pixel electrode
106
.
Liquid crystal layer
102
rotates the polarization of light passing through it, the degree of rotation depending on the root-mean-square (RMS) voltage across liquid crystal layer
102
. The ability to rotate the polarization is exploited to modulate the intensity of reflected light as follows. An incident light beam
122
is polarized by polarizer
124
. The polarized beam then passes through liquid crystal layer
102
, is reflected off of pixel electrode
106
, and passes again through liquid crystal layer
102
. During this double pass through liquid crystal layer
102
, the beam's polarization is rotated by an amount which depends on the data signal being asserted on pixel storage electrode
106
. The beam then passes through polarizer
126
, which passes only that portion of the beam having a specified polarity. Thus, the intensity of the reflected beam passing through polarizer
126
depends on the amount of polarization rotation induced by liquid crystal layer
102
, which in turn depends on the data signal being asserted on pixel storage electrode
106
.
Storage element
108
can be either an analog storage element (e.g. capacitative) or a digital storage element (e.g., SRAM latch). In the case of a digital storage element, a common way to drive pixel storage electrode
106
is via pulse-width-modulation (PWM). In PWM, different gray scale levels are represented by multi-bit words (i.e., binary numbers). The multi-bit words are converted to a series of pulses, whose time-averaged root-mean-square (RMS) voltage corresponds to the analog voltage necessary to attain the desired gray scale value.
For example, in a 4-bit PWM scheme, the frame time (time in which a gray scale value is written to every pixel) is divided into 15 time intervals. During each interval, a signal (high, e.g., 5V or low, e.g., 0V) is asserted on the pixel storage electrode
106
. There are, therefore, 16 (0-15) different gray scale values possible, depending on the number of “high” pulses asserted during the frame time. The assertion of 0 high pulses corresponds to a gray scale value of 0 (RMS 0V), whereas the assertion of 15 high pulses corresponds to a gray scale value of 15 (RMS 5V). Intermediate numbers of high pulses correspond to intermediate gray scale levels.
FIG. 2
shows a series of pulses corresponding to the 4-bit gray scale value (
1010
), where the most significant bit is the far left bit. In this example of binary-weighted pulse-width modulation, the pulses are grouped to correspond to the bits of the binary gray scale value. Specifically, the first group B
3
includes 8 intervals (2
3
), and corresponds to the most significant bit of the value (
1010
). Similarly, group B
2
includes 4 intervals (2
2
) corresponding to the next most significant bit, group B
1
includes 2 intervals (2
1
) corresponding to the next most significant bit, and group B
0
includes 1 interval (2
0
) corresponding to the least significant bit. This grouping reduces the number of pulses required from 15 to 4, one for each bit of the binary gray scale value, with the width of each pulse corresponding to the significance of its associated bit. Thus, for the value (
1010
), the first pulse B
3
(8 intervals wide) is high, the second pulse B
2
(4 intervals wide) is low), the third pulse B
1
(2 intervals wide) is high, and the last pulse B
0
(1 interval wide) is low. This series of pulses results in an RMS voltage that is approximately
2
3
(10 of 15 intervals) of the full value (5V), or approximately 4.1V.
FIG. 3
shows 3 pixel cells
100
(
a-c
) arranged adjacent one another, as in a typical flat panel display. Problems arise in such displays, because differing signals on adjacent pixel cells can cause visible artifacts in a display image. For example, electrical field lines
302
indicate that logical high signals are being asserted on each of pixel electrodes
106
(
a
and
c
). The absence of an electrical field across pixel cell
100
(
b
) indicates that a logical low signal is being asserted on pixel electrode
106
B. Note that in addition to the electrical fields
302
across liquid crystal layers
102
(
a
and
c
), transverse fields
304
exist between pixel electrodes
106
(
a
and
c
), carrying a logical high signal, and pixel electrode
106
(
b
), carrying a logical low signal. Transverse fields
304
affect the polarization rotation of the light passing through liquid crystal layers
102
(
a-c
), and therefore, potentially introduce visible artifacts.
Whether, and to what extent, visible artifacts are produced between adjacent pixel cells depends on the time period that logically opposite signals (i.e., high and low) are asserted on adjacent pixel electrodes. Adjacent pixel cells carrying opposite signals are said to be out of phase. The percentage of the total frame time that adjacent pixel cells are out of phase is referred to herein as the phase difference between the adjacent cells. Visible artifacts are most noticeable when adjacent pixel cells are written with gray values that are close in intensity, but have a large phase difference.
FIG. 4
is a table showing the bit values and phase differences between selected gray scale values in an eight-bit, binary-weighted, pulse-width modulation scheme. Note that gray values
127
and
128
, while having an intensity difference of only one level, have a phase difference of 100%, and thus result in a visible artifact when written to adjacent pixel cells. Similarly, gray values 63 and 64 (as well as gray values 191 and
192)
have a phase difference of 127/255, which also causes unacceptable image artifacts.
What is needed is a system and method for reducing the maximum possible phase difference between gray scale values asserted on adjacent pixel electrodes.
SUMMARY
A novel system and method for reducing the maximum possible phase difference between data asserted on adjacent pixel electrodes is described. The system and method employ compound data words, which comprise a first group of bits that are each asserted on a display pixel for a coequal time period, and a second group of bits that are asserted on the display pixel for a time period dependent on their significance. The maximum phase difference between adjacent gray scale values (e.g., gray scale value 79 and gray scale value 80) is thereby limited to one of the bits of the first group and all of the bits of the second group being out of phase.
In one embodiment of the invention, a display driver circuit includes an output controller configured to provide display control signals which cause each bit of the first group of data bits to be asserted on a display pixel for a coequal time period. The control signals also cause each bit of the second group of data bits to be asserted on the pixel for a time period that depends on an associated significance of each bit. Thus, each bit of the first group is asserted for a time period equal to the time period that the other bits of the first group are asserted, and each bit of the second group is asserted for a time period different than the other bits of the second group. In a particular embodiment, the length of each coequal time period is twic
Aurora Systems, Inc.
Henneman & Saunders
Henneman, Jr. Larry E.
Liang Regina
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