Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using shift register
Reexamination Certificate
1999-04-23
2001-10-09
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Using shift register
C377S026000, C377S073000, C377S078000, C377S080000, C365S230080, C365S233100, C365S240000, C326S094000, C327S292000, C327S296000
Reexamination Certificate
active
06301322
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit devices, and more particularly, to a bit shifting circuit and method used in memory devices.
BACKGROUND OF THE INVENTION
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of such a SLDRAM memory device is shown in FIG.
1
. The memory device
30
includes a clock generator circuit
40
that receives a command clock signal CMDCLK and generates an internal clock signal ICLK and a large number of other clock and timing signals to control the timing of various operations in the memory device
30
. The memory device
30
also includes a command buffer
46
and an address capture circuit
48
, which receive the internal clock signal ICLK, a command packet CA
0
-CA
9
on a 10-bit command bus
50
, and a FLAG signal on line
52
. A memory controller (not shown) or other device normally transmits the command packet CA
0
-CA
9
to the memory device
30
in synchronism with the command clock signal CMDCLK. As explained above, the command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence. The command buffer
46
receives the command packet from the bus
50
, and compares at least a portion of the command packet to identifying data from an ID register
56
to determine if the command packet is directed to the memory device
30
or some other memory device (not shown). If the command buffer
46
determines that the command packet is directed to the memory device
30
, it then provides the command words to a command decoder and sequencer
60
. The command decoder and sequencer
60
generates a large number of internal control signals to control the operation of the memory device
30
during a memory transfer.
The address capture circuit
48
also receives the command words from the command bus
50
and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer
64
, which generates a corresponding 3-bit bank address on bus
66
, a 10-bit row address on bus
68
, and a 7-bit column address on bus
70
. The column address and row address are processed by column and row address paths
73
,
75
as will be described below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM
30
shown in
FIG. 1
largely avoids this problem by using a plurality of memory banks
80
, in this case eight memory banks
80
a-h
. After a read from one bank
80
a
, the bank
80
a
can be precharged while the remaining banks
80
b-h
are being accessed. Each of the memory banks
80
a-h
receives a row address from a respective row latch/decoder/driver
82
a-h
. All of the row latch/decoder/drivers
82
a-h
receive the same row address from a predecoder
84
which, in turn, receives a row address from either a row address register
86
, redundant row circuit
87
, or a refresh counter
88
, as determined by a multiplexer
90
. However, only one of the row latch/decoder/drivers
82
a-h
is active at any one time, as determined by bank control logic
94
as a function of a bank address from a bank address register
96
.
The column address on bus
70
is applied to a column latch/decoder
100
, which supplies I/O gating signals to an I/O gating circuit
102
. The I/O gating circuit
102
interfaces with columns of the memory banks
80
a-h
through sense amplifiers
104
. Data is coupled to or from the memory banks
80
a-h
through the sense amplifiers
104
and the I/O gating circuit
102
and a data path subsystem
108
, which includes a read data path
110
and a write data path
112
. The read data path
110
includes a read latch
120
that stores data from the I/O gating circuit
102
. In the memory device
30
shown in
FIG. 3
, 64 bits of data are stored in the read latch
120
.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Wambach Margaret R.
LandOfFree
Balanced dual-edge triggered data bit shifting circuit and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Balanced dual-edge triggered data bit shifting circuit and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Balanced dual-edge triggered data bit shifting circuit and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2566123