Testing Board

Details Testing Board Testing Board

1999-07-14

2001-05-15

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S755090

Reexamination Certificate

active

06232791

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a testing board for testing the electric characteristics of semiconductor integrated circuit elements by applying a voltage to each of the testing electrodes of the semiconductor integrated circuit elements.
In the process of fabricating a conventional semiconductor integrated circuit device, an electrical connection is provided between a semiconductor chip and a leadframe by a bonding wire and then the semiconductor chip and the leads of the leadframe are sealed with a resin or ceramic to be mounted on a printed circuit board.
To meet the demand for an electronic device reduced in both size and price, there has been developed a method of mounting, on a circuit board, a semiconductor integrated circuit element as a bare chip cut out of a semiconductor wafer. The bare chip used in the method is preferably a quality-assured bare chip supplied at lower price.
In accordance with a known testing method, a burn-in process is performed with respect to semiconductor integrated circuit elements by using a testing board having probe terminals to be connected to the testing electrodes of the semiconductor integrated circuit elements.
FIGS. 5 and 6
show a testing board that has been proposed for use in the testing method.
One type of testing board to be provided by the present invention is for performing a wafer-level test with respect to a plurality of semiconductor integrated circuit elements formed in a semiconductor wafer such that the electric characteristics thereof are tested simultaneously. The other type of testing board to be provided by the present invention is for individually testing the electric characteristics of semiconductor packages having semiconductor integrated circuit elements (semiconductor chips) cut out of a semiconductor wafer and covered with resin packages.
FIG. 5
shows a cross-sectional structure of a testing board for performing a wafer-level test with respect to a plurality of semiconductor integrated circuit elements formed in a semiconductor wafer such that the electric characteristics thereof are tested simultaneously. In this case,
FIG. 6
shows an enlarged cross-sectional structure of the portion enclosed in the dot-dash box in FIG.
5
.
As shown in
FIGS. 5 and 6
, a large number of testing electrodes
2
are provided on the surface of a semiconductor wafer
1
formed with a plurality of semiconductor integrated circuit elements. The peripheral portions of the testing electrodes
2
are covered with a passivation film
3
.
As shown in
FIG. 5
, a ring-shaped seal member
5
composed of an elastic material is provided around a wafer mount portion
4
a
of a wafer tray
4
for holding the semiconductor wafer
1
. An open/close valve
6
is provided at an appropriate portion of a side surface of the wafer tray
4
to be connected to evacuating means not shown. A ring-shaped evacuation groove
7
connecting to the open/close valve
6
is formed between the wafer mount portion
4
a
of the wafer tray
4
a
and the seal member
5
.
A testing board E is provided in opposing relation to the semiconductor wafer
1
held by the wafer tray
4
. The testing board E comprises: a wiring board
50
having a wiring layer
50
a
; an elastic sheet
52
composed of, e.g., a polyimide sheet fixed to the wiring board
50
by means of a rigid ring
51
; hemispherical probe terminals
53
disposed on the elastic sheet
52
to correspond to the testing electrodes
2
on the semiconductor wafer
10
; and an anisotropic conductive rubber sheet
54
for providing an electric connection between one end of the wiring layer
50
a
of the wiring board
50
and each of the probe terminals
53
. As shown in
FIG. 6
, numerous conductive particles
55
are provided within the anisotropic conductive rubber sheet
54
in mutually connected relation, whereby electric connections are provided between the wiring layer
50
a
of the wiring board
50
and the probe terminals
53
.
The other end of the wiring layer
50
a
of the wiring board
50
is connected to a testing apparatus for supplying a testing voltage such as a power-source voltage, a ground voltage, or a signal voltage, which is not shown.
As stated previously, in the case where a wafer-level test is performed simultaneously with respect to the plurality of semiconductor integrated circuit elements in the semiconductor wafer
1
, a sealed space
56
is defined by the wafer tray
4
, the seal member
5
, and the elastic sheet
52
if the wafer tray
4
a
and the wiring board
50
are brought closer to each other. If the sealed space
56
is evacuated via the open/close valve
6
connected to the evacuating means not shown, the wafer tray
4
a
and the elastic sheet
52
are brought much closer to each other, which provides an electric connection between each of the testing electrodes
2
on the semiconductor wafer
1
and the corresponding probe terminal
53
. Thereafter, a testing voltage is applied from the testing apparatus to each of the testing electrodes
2
on the semiconductor wafer
1
and an output signal from each of the testing electrodes
2
is inputted to the testing apparatus, whereby each of the semiconductor integrated circuit elements formed on the semiconductor wafer
1
is tested for electric characteristics by the testing apparatus.
When the testing electrodes
2
on the semiconductor wafer
1
and the corresponding probe terminals
53
are brought into contact with each other by evacuating the sealed space
56
, a problem arises if the heights of the testing electrodes
2
or probe terminals
53
vary. However, since the height variations can be accommodated by elastic deformation of the anisotropic conductive rubber sheet
54
interposed between the wiring layer
50
a
of the wiring board
50
and the probe terminals
53
, an electric connection is provided reliably between each of the testing electrode
2
on the semiconductor wafer
1
and the corresponding probe terminal
53
of the testing board E.
As described above, electrical continuity between the wiring layer
50
a
of the wiring board
50
and the probe terminals
53
is produced by the numerous conductive particles
55
disposed within the anisotropic conductive rubber sheet
54
, so that the resistance of the anisotropic conductive rubber sheet
54
is determined by the filling factor of the conductive particles
55
. However, variations in the filling factor of the conductive particles
55
cause variations in the resistance of the anisotropic conductive rubber sheet
54
, which necessitates a difficult operation for controlling the filling factor of the conductive particles
55
.
Moreover, a small contact area between the conductive particles
55
makes it difficult to reduce the resistance of the anisotropic conductive rubber sheet
54
a
and therefore the contact resistance between the wiring layer
50
a
of the wiring board
50
and the probe terminals
53
.
As stated previously, the sealed space
56
should be evacuated with a large evacuation force to ensure contact between each of the testing electrodes
2
of the semiconductor wafer
1
and the corresponding probe terminal
53
of the testing board E. The evacuation of the sealed space
56
is performed repeatedly every time the semiconductor wafer
1
is tested and a load is repeatedly placed on the anisotropic conductive rubber sheet
54
on each evacuation. Consequently, the anisotropic conductive rubber sheet
54
is plastically deformed and reliable contact is no more provided between the testing electrodes
2
and the probe terminals
53
or the arrangement of the numerous conductive particles
55
provided within the anisotropic conductive rubber sheet
54
a
is disordered, which varies the resistance between the wiring layer
50
a
and the probe terminal
53
.
Since the higher integration of the semiconductor integrated circuit elements formed in the semiconductor wafer
1
reduces the pitch of the adjacent testing electrodes
2
and therefore the pitch of adjacent rows in which the conductive particles
55
provid

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