Delay locking using multiple control signals

Details Delay locking using multiple control signals Delay locking using multiple control signals

1997-06-25

2001-02-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000, C331S042000

Reexamination Certificate

active

06194929

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to circuitry for generating periodic signals such as clock signals, and, more particularly, to delay lock loops (DLLs).
2. Description of the Related Art
Many high speed electrical systems possess critical timing requirements which dictate the need to generate a periodic clock wave form that possesses a precise time relationship with respect to some reference signal.
Conventionally, a phase-locked loop (PLL) which employs a voltage control oscillator (VCO) is used to provide the desired clock signal. An example of a PLL is shown in
FIG. 1
a
. The classic PLL includes a phase detector, a filter, and a voltage-controlled oscillator (VCO). The PLL phase detector is a device that compares two input frequencies of an external clock and an internal clock (from the VCO), and generates an output that is a measure of their phase difference. For example, if there is a difference in frequency, the phase detector generates a periodic output at the difference frequency. If the frequency of the external clock does not equal the frequency of the internal clock, the phase-error signal, after being filtered and amplified, causes the VCO frequency to deviate in the direction of the external clock frequency. Under the proper conditions, the VCO will lock to the external clock frequency to maintain a fixed phase relationship with the external clock.
While VCO-based PLLs have been used successfully to provide compensation for a variety of timing errors, VCO-based PLLs have some undesirable characteristics. For example, acquisition of the desired timing relationship which requires multiple iterations of signal through the PLL is often slow (typically many hundreds or thousands of clock cycles) because of the time required to drive the VCO to the correct frequency. PLLs often overshoot the target frequency a number of times before locking at the target frequency. Furthermore, designing VCOs with ample power supply rejection characteristics is difficult, particularly when implementing circuitry in CMOS, as power supply voltages utilized in such circuitry are designed to be lower and lower to conserve power.
An alternative PLL circuit is the delay locked loop (DLL) which generates an output signal a predetermined delay from the input reference signal. An example of a DLL is shown in
FIG. 1
b
. A typical DLL includes a phase detector and filter like a PLL. However, the DLL includes a phase shifter instead of a VCO. The DLL corrects a detected phase difference by placing the edges of an internal clock of the proper frequency. In other words, the DLL corrects phase instead of frequency, unlike a VCO. An exemplary DLL is described in U.S. Pat. No. 5,614,855, entitled “Delay-Locked Loop,” naming Thomas H. Lee, Kevin S. Donnelly, Tsyr-Chyang Ho and Mark G. Johnson as inventors, which is incorporated herein by reference.
DLLs have traditionally had limited phase shift capability and certain metastability problems. The system in which a DLL is used must typically be limited so that the DLL is never driven into the limit of its phase shift capability. Furthermore, DLLs typically include a single control voltage for selecting among clock phases. For example, a control voltage swings between a minimum voltage and a maximum voltage. The control voltage selects all of a first clock at the minimum voltage and all of a second quadrature clock at the maximum voltage. At intermediate voltages, the control voltage selects portions of each of the clocks. In this way, the control voltage selects for as much as 90° of phase difference. In order to select for further phase difference, a negative of one of the quadrature clocks is digitally selected. However, there can be certain metastability problems due to circuit setup times and accumulated phase-error signals.
SUMMARY
It has been discovered that by using a plurality of control voltages, a more stable method and circuit for generating a periodic clock wave form that possesses a precise time relationship with respect to some reference signal is provided.
In one embodiment of the present invention, a delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error input signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error input signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase. The phase shift circuit applying the control input signals to select from among the periodic input signals to generate a periodic output signal. The periodic output signal being one of the first and second signals.
In another embodiment of the present invention, a method of determining phase selection signal values in a delay-locked loop is provided. The method includes receiving a reference input signal and a periodic input signal; generating a phase-error signal indicating whether the periodic input signal is slower than or faster than the reference input signal; and generating a plurality of control signals for selecting from among a plurality of internal periodic signals. Each of the internal periodic signals have a different phase. Each of the control signals are based upon a signal derived from the phase-error signal and by at least one signal derived from at least one other of the control signals. The method includes applying signals derived from the control signals to generate an output periodic signal from which the periodic input signal is derived. The output periodic signal is generated in a predetermined timing relationship with the reference input signal by selecting from among the plurality of internal periodic signals.


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S. Sidiropoulos, M. Horowitz, “A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” IEEE Intl Solid-State Circuits Conference Digest of Technical Papers, 1997, pp. 332-333 and accompanying Figure 6.

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