Integrated circuit with removable ESD protection

Details Integrated circuit with removable ESD protection Integrated circuit with removable ESD protection

1999-12-22

2001-12-04

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06327125

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is in the field of integrated circuits (“ICs”), and more particularly, solves a problem posed by the inclusion of electrostatic discharge (“ESD”) protection circuits within integrated circuits.
2. Description of the Prior Art
Integrated circuits are susceptible to damage when they are subjected to electrostatic discharge (ESD), more commonly known as “static electricity”. While the discharge of static electricity can be a “shocking” experience for humans, the effect is usually fleeting. However, the effect on an IC can be permanent. The energy from the discharge of static electricity can be enough to vaporize conductor paths in an IC, causing the IC to be completely inoperable, to function in an unpredictable way, or to create defects which shorten the life of the IC. ESD events can occur at any time during the life of the part but most events that cause damage occur between the time that the circuit is manufactured in wafer form and the time that the circuit is physically mounted in the circuit board that connects the integrated circuit into the system where it is to be used.
ICs are usually protected from ESD damage by including extra device structures that are designed to absorb the ESD events while not causing an undue effect on the performance of the circuit. These structures can be as simple as a fuse or diode, or more complicated, such as grounded NMOS transistors or bipolar transistors in latchback configuration. For high performance, high frequency applications, the capacitance of the ESD protection circuitry can be the limiting factor on the performance of the circuit.
U.S. Pat. No. 5,731,945 (Bertin et al) discloses a multichip integrated structure in which various IC wafers are bonded together to form a single unitary structure. Conductors on side surfaces of the wafers electrically couple the circuits on adjoining wafers. Bertin discloses how to disconnect redundant circuitry in individual wafers of the bonded pre-encapsulated structure, including redundant ESD protection to reduce the overall capacitive loading. Bertin indicates that in some instances, only one ESD circuit need be coupled in circuit to provide ESD protection for the entire multi-wafer bonded IC structure. Bertin discloses the use of fuses, antifuses, etching techniques, and focused ion beam personalization for ESD customization prior to packaging of the multi-wafer structure. Bertin further discloses the use of active circuitry, such as transistor pass gates, to selectively decouple ESD protection from I/O nodes after an IC has been packaged and installed in a system.
A disadvantage of Bertin's structure is that deselection of ESD circuits by fusing and selective wiring is done after the wafers are bonded to each other, but prior to encapsulation. A disadvantage of Bertins structure with respect to active circuit control is the complication of adding internal control circuitry to activate the switching transistors. Furthermore, the switching transistor, even if selected to be of low capacitance, still burdens the I/O nodes. Additionally, ESD protection and its associated loading are still provided to protect the selection node that provides the selection signal to the ESD selection transistor.
SUMMARY OF THE INVENTION
Generally speaking, according to one aspect of the invention, an integrated circuit includes an operational circuit coupled between first and second supply rails. An ESD protection circuit and fuse are also coupled in series between the supply rails. External connection pins include a first external connection pin coupled to the first rail, a second external connection pin coupled to the second rail, and a third external, program pin coupled to a node between the fuse and the ESD protection circuit. The fuse is programmable to create an open circuit between the ESD protection circuit and one of the supply rails by connecting the third program pin to an appropriate source of electric potential.
The above integrated circuit has the advantage that the ESD protection provided by the ESD protection circuit is easily disconnectable at any time after packaging of the IC is completed simply by providing a suitable electric potential at the external program pin to blow the fuse and create an open circuit. Thus, the ESD protection may remain in place during the IC's long journey from handling of the completed wafer in the IC fab area, packing and shipping to the location where the wafer will be encapsulated in an IC package and provided with external connection pins, and finally during shipping to the customer and handling by the customer to assemble the completed IC in a system. At a desired step in the assembly of the IC in the system, when significant threat of ESD damage has subsided, the customer may remove the ESD protection simply by providing an appropriate potential to the ESD program pin.
Advantageously, at the time of assembly into the system, by coupling the program pin to the connection pin coupled to the opposite rail than that to which the fuse is connected, the fuse will simply be blown the first time the power is applied in the system.
Furthermore, the technique requires only very simple structure in the IC, namely extra conductor lines and a minimal number of fuses. By keeping the conductor lines short, the extra capacitive loading imposed on the I/O pads/pins or operational circuitry after the fuses are opened is substantially zero. This structure has significantly lower capacitance than the use of active switches, such as the pass gate disclosed in Bertin. No additional ESD protection circuit is needed for the control gate of an active device to prevent the active device from inadvertently prematurely disconnecting the primary ESD circuits, as disclosed in Bertin.
Another aspect of the invention relates to ESD protection, and removal thereof, for I/O paths of the IC. In this embodiment, the IC includes a pair of fuses each coupled to a respective supply rail and a pair of ESD protection circuits for each pin coupled in series with the fuses (see FIG.
1
). An I/O connection pin is coupled between the first and second ESD protection circuits and a fourth external, program pin is coupled to the second fuse. The first and second fuses are programmable to create an open circuit between each respective supply rail and the respective ESD protection circuit by coupling each of the third and fourth program pins to appropriate potentials, to thereby eliminate loading of the I/O pin by the first and second ESD protection circuits. Favorably, any further I/O pins which have ESD protection have their ESD protection circuits coupled between the first and second fuses so that all ESD protection circuits are disconnected when the first and second fuses are opened. Thus, all ESD circuits coupled to the output pins are removed with only two extra pins and two fuses.
These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings.


REFERENCES:
patent: 5341267 (1994-08-01), Whitten
patent: 5731945 (1998-03-01), Bertin et al.
patent: 5757590 (1998-05-01), Phipps et al.
patent: 6141245 (2000-10-01), Bertin et al.
patent: 0589519A2 (1994-03-01), None

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