Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-28
2001-12-04
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S051000, C365S063000
Reexamination Certificate
active
06327179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device having electrically rewritable nonvolatile memory cells having two-layer gate structure, and a method for producing the same. More specifically, the invention relates to the improvement of a process when peripheral circuits, such as logic circuits, are consolidated into a semiconductor memory device.
2. Related Background Art
A typical memory transistor of a nonvolatile semiconductor memory, such as an EEPROM, has a floating gate, which is formed on a semiconductor substrate via a gate insulating film, and a control gate which is formed on the floating gate via an insulating film. The memory transistor is combined with a selecting gate transistor to constitute a memory cell. In this case, the gate electrode of the selecting gate transistor is formed of the same gate electrode material film as that of the floating gate of the memory cell. In addition, when logic circuits, together with nonvolatile memory cells, are integrated to be formed, the gates of logic circuit transistors are formed of the same gate electrode material film as those of the control gates of the memory cells.
The semiconductor substrate, on which the memory cells and the logic circuit transistors have been formed, is covered with an interlayer dielectric film, and a metal wiring is formed thereon. The planarization of the interlayer dielectric film underlying the wiring is indispensable to the fine patterning of the wiring. In particular, when the wiring is formed in multilayer, the planarization of the interlayer dielectric film is indispensable. In recent years, the CMP (Chemical Mechanical Polishing) technique is often used for carrying out the planarization of the interlayer dielectric film.
When the planarization of the interlayer dielectric film is carried out by the CMP process, it is desired that the difference between the level of the two-layer gate structure portion of a memory cell array region and the level of the one-layer gate structure portion of a logic circuit is smaller from the point of view of the margin of contact and the prevention of short-circuit accident. In order to achieve this, it is considered that the first-layer gate electrode material film of the memory transistor and selecting gate transistor is thinned.
However, if the first-layer gate electrode material film is thin, the contact of the metal wiring easily goes through the gate electrode of the selecting gate transistor which is formed of the first-layer gate electrode material film. This causes the deterioration of yields and the deterioration of reliability due to the contact failure of the metal wiring to the selecting gate transistor.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device capable of improving yields and reliability using a three-layer gate electrode material film, and a method for producing the same.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array having arranged memory transistors and selecting gate transistors of nonvolatile memory cells,
each the memory transistor and each the selecting gate transistor having a first-layer gate electrode material film, which is formed on a semiconductor substrate via a gate insulating film, and second-layer and third-layer gate electrode material films which are stacked on the first-layer gate electrode material film via an interlayer dielectric film,
each the memory transistor having a floating gate, which is formed of the first-layer electrode material film, and a control gate which is formed of a laminated film of the second-layer and third-layer gate electrode material films, and
each the selecting gate transistor having a gate electrode which is formed of the first-layer to third-layer electrode material films while the third-layer gate electrode material film contacts the first-layer gate electrode material film via an opening which is formed in the second-layer gate electrode material film and the interlayer insulating film.
According to another aspect of the present invention, there is provided a method for producing a semiconductor memory device wherein a memory cell array and a peripheral circuit are integrated on a semiconductor substrate, the method comprising:
a first step of depositing a first-layer gate electrode material film on the semiconductor substrate via a first gate insulating film;
a second step of depositing an interlayer dielectric insulating film on said first-layer gate electrode material film;
a third step of etching and removing the interlayer insulating film and said first-layer gate electrode material film on the semiconductor substrate in a peripheral circuit forming region;
a fourth step of forming a second gate insulating film on the semiconductor substrate in the peripheral circuit forming region;
a fifth step of depositing a second-layer gate electrode material film on the interlayer insulating film and the second gate insulating film;
a sixth step of forming an opening which passes through the second-layer gate electrode material film and the interlayer insulating film to the first-layer gate electrode material film, in a selecting gate transistor region of the memory cell array;
a seventh step of depositing a third-layer gate electrode material film so as to be stacked on the second-layer gate electrode material film; and
an eighth step of sequentially etching the third-layer gate electrode material film, the second-layer gate electrode material film, the interlayer insulating film and the first-layer gate electrode material film, to form memory transistors and selecting gate transistors in the memory cell array region, each the memory transistor has a floating gate of the first-layer gate electrode material film and a control gate of a laminated film of the second-layer and third-layer gate electrode material films, each the selecting gate transistor having a first gate electrode wherein the third-layer gate electrode material film contacts the first-layer gate electrode material film via the opening, and to form transistors in the peripheral circuit forming region each of which transistor has a second gate electrode of the laminated film of the second-layer and third-layer gate electrode material films.
According to the present invention, the gate electrode of the selecting gate transistor is formed by patterning the first-layer gate electrode material film and the third-layer gate electrode material film contacting therewith. Therefore, even if the first-layer gate electrode material film is thin, it is possible to surely prevent the metal wiring from going through the gate electrode of the selecting gate transistor at the step of bringing the metal wiring into contact with the gate electrode of the selecting gate transistor, so that it is possible to improve yields and reliability.
In addition, the control gate of the memory transistor is formed of the laminated film of the second-layer and third-layer gate electrode material films, and the gate electrode of the peripheral circuit transistor is also formed of the laminated film of the second-layer and third-layer gate electrode material films. Therefore, by thinning the first-layer gate electrode material film, it is possible to decrease the difference between the levels of the gate portions of the memory transistor and the peripheral transistor, so that it is possible to easily carry out the planarization of the interlayer dielectric film before forming the metal wiring.
REFERENCES:
patent: 5298775 (1994-03-01), Ohya
Fears Terrell W.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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