Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-01-28
2001-10-16
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C324S1540PB
Reexamination Certificate
active
06304092
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a self-aligning docking assembly for a semiconductor tester.
A semiconductor integrated circuit (IC) tester typically includes a test head having a test head body which accommodates pin electronics for carrying out test activities at each of a plurality of terminals of the pin electronics. Such a tester can be used in conjunction with a wafer prober for testing semiconductor integrated circuits embodied in a wafer prior to dicing of the wafer into individual integrated circuit chips. The wafer prober includes a docking plate which is formed with a circular hole and an insert ring is loosely fitted in the hole in the docking plate. Two docking bars are attached to the docking plate so that the hole in which the insert ring is fitted is between the docking bars. The insert ring and the docking bars are parts of a mechanical interface between a particular wafer prober and a particular test head. A probe card is located in the insert ring and is aligned relative to the insert ring by engagement of alignment bores of the probe card with alignment pins of the insert ring. The probe card has probe wires for engaging contact pads of at least one chip. The wafer prober also includes a mechanism for bringing successive wafers to a test station, adjusting the position of the wafer at the test station stepwise to permit engagement of the probe wires successively with all the chips of the wafer and then removing the wafer from the test station to allow another wafer to be positioned at the test station.
The test head includes a load board and a so-called pogo tower, which accommodates an array of pogo pins. A traction mechanism pulls the test head towards the docking plate along a Z axis and the test head is positioned relative to the wafer prober along X and Y axes by engagement of alignment pins carried by the test head with alignment bores formed in the docking bars. When the test head is properly docked with the wafer prober, the insert ring is aligned relative to the test head body with a high degree of precision and the terminals of the pin electronics are electrically coupled to the probe wires of the probe card through the load board and the pogo tower.
A small tolerance is permitted in relative positioning of the docking bars relative to the docking plate, because the mechanism used for positioning the wafer allows minor adjustment in the XY position of the wafer, but it is important that the docking bars be accurately positioned relative to each other since otherwise the alignment pins of the test head will not properly engage the alignment bores of the docking bars and the test head will not be brought to the proper position relative to the docking plate. Adjustment in the relative positions of the docking bars is generally accomplished using a calibration bar having alignment pins which engage the alignment bores of the docking bars. Thus, prior to engagement of the test head with the wafer prober, the calibration bar is applied to the docking bars while the docking bars are attached loosely to the docking plate. The docking bars are brought to the correct relative positions with the aid of the calibration bar and are then secured tightly to the docking plate. When the test head is properly engaged with the docking bars, the pogo pins engage the probe card.
Several different calibration bars may be needed for positioning the docking bars of a given wafer prober, depending on the tester with which the prober is being used at the time. Further, because of minor design changes in testers and wafer probers, the calibration bar for a given combination of wafer prober and tester might not be usable with another wafer prober of the same model and/or another tester of the same model. Consequently, in a large testing facility, there may be a need for numerous calibration bars which appear very similar but are in fact different. If one of the calibration bars should be lost or damaged, it would generally be necessary to make another calibration bar, and this is a time consuming and expensive operation.
In the conventional wafer prober, the insert ring is not constrained relative to the docking bars except by virtue of both the insert ring and the docking bars being constrained relative to the docking plate. When the test head is docked with the wafer prober, the insert ring is precisely positioned relative to the docking bars by virtue of both the insert ring and the docking bars being precisely positioned relative to the test head.
SUMMARY OF THE INVENTION
In accordance with the invention there is provided apparatus for testing semiconductor integrated circuit devices, comprising a wafer prober including a docking plate, a semiconductor integrated circuit tester including a test head, and a mechanical interface between the test head and the wafer prober, the mechanical interface including docking bars, a releasable means for attaching the docking bars to the docking plate, and an interface member between the test head and the docking plate, and wherein the test head has a body, a terminal support structure for positioning terminals of the test head relative to the body of the test head, alignment elements for engaging the docking bars if the docking bars are in predetermined relative positions for ensuring that the body of the test head is properly positioned relative to the docking bars, and an attachment mechanism for securing the test head to the wafer prober, and wherein the interface member and the docking bars have complementary alignment features which can be brought into engagement and, when so engaged, ensure that the docking bars are in said predetermined relative positions.
REFERENCES:
patent: 5489853 (1996-02-01), Nakajima
patent: 5656943 (1997-08-01), Montoya et al.
patent: 5670889 (1997-09-01), Okubo et al.
Credence Systems Corporation
Karlsen Ernest
Smith-Hill John
Smith-Hill and Bedell
Tang Minh
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