Method of molding a bump chip carrier and structure made...

Details Method of molding a bump chip carrier and structure made... Method of molding a bump chip carrier and structure made...

2000-02-01

2001-10-23

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S122000, C438S124000

Reexamination Certificate

active

06306685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of molding a bump chip carrier, more particularly, to a method of molding a bump chip carrier, which reduces the manufacturing steps and the manufacturing time and allows a relatively thin and lighter chip having better exothermic characteristics to
2. Description of Related Art
A conventional bump chip carrier molding method shown in
FIG. 5
comprises the steps listed below.
First as shown in A of
FIG. 5
, provide a copper base plate (
80
) having a thickness suitable for carrying a die, preferably a thickness of at least 10 mil.
As shown in B of
FIG. 5
, half-etch the copper base plate (
80
) to prepare connection cavities (
81
). The term “half-etching” refers to etching the copper base plate to a depth of half the thickness of the etched copper base plate without totally penetrating the copper base plate.
Then, as shown in C of
FIG. 5
, multiple plate (in the sequence of) Gd, Pd, Ni, and Pd into each connection cavity (
81
) (see
FIG. 6
) to form a metallized connection point (
83
) used for connecting a die to components located outside.
As shown in D of
FIG. 6
, then fixedly mount a die (
82
) on the central part of the copper base plate (
80
) and connect the die (
82
) to each metallized connection point (
83
) with bonding wires.
As shown in E of
FIG. 5
, apply a molding layer (
84
) to the top surface of the copper base plate (
80
).
As shown in F of
FIG. 5
, etch out the excessive parts of the copper base plate (
80
) completely so that the bottom of the die (
82
) and the metallized connection points (
83
) are exposed from the bottom surface of the molding layer (
84
).
As shown in G of
FIG. 5
, plate an exothermal metal passage (
85
) to the bottom surface of the die (
82
).
Though this conventional method solves many problems involved in the molding of the bump chip carrier, some difficulties are still found in it:
1. It is not easy to precisely control the half-etching process, since the requirements for the half-etching process in terms of precision are very critical. The conventional method employs the half-etching process to form the connection cavities used for forming metallized connection points. However, it is not easy to control the etching depth in such a process. Therefore, if the half-etching process is not controlled well enough, either insufficient or excessive etching will occur and adversely affect the quality of molding thereby increasing the manufacturing cost.
3. The manufacturing cost is too high. Since the half-etching step is employed, the thickness of the copper base plate (
80
) for carrying the die (
82
) should be limited to a certain range. In practice, this thickness of the copper base plate (
80
) is over 10 mil. In addition, the copper base plate (
80
) must be totally etched out. Therefore, the cost for the copper base plate used will be very high due to the large thickness requirements of the copper base plate (
80
), and an unnecessary waste of copper material will occur due to totally etching out the copper base plate (
80
).
4. The manufacturing steps are excessive. To form the metallized connection points in accordance with the conventional method involves four plating procedures resulting in both excessive steps and long manufacturing time.
Therefore, there is still a need to resolve the above-mentioned problems and difficulties.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a method of molding a bump chip carrier, which reduces the manufacturing steps and the manufacturing time and allows a relatively thin and lighter die having better exothermic characteristics to be packaged.
To achieve the objective, the method of molding a bump chip carrier in accordance with the present invention comprises the following steps.
Applying dry films: apply dry films to the top and bottom surfaces of a copper base plate having a suitable thickness.
Forming a circuit pattern on each of the dry films: form a circuit pattern on each of the dry films by using a photo engraving process.
Plating: plate variable metals (arranged in a desired sequence) onto each of the circuit patterns to form a connection pad.
Remove the dry films.
Mounting and wire-bonding a die: fixedly mount a die on the copper base plate and bond the die to the connection pads with wires.
Molding: mold one of the surfaces of the copper base plate to form a molding layer.
Removing excessive parts of the copper base plate: etch out the excessive parts of the copper base plate situated under the bottom face of the molding layer.
The connection pads and the exothermal metal passage can be formed at the same time in the method in accordance with the present invention to effectively reduce the cost and allow a relatively light and thin chip to be made thereby.
In the step of “forming circuit patterns”, the circuit pattern of the connection pad for connecting the die can be transferred to the dry film under the bottom surface of the copper base plate, while, most preferably, the circuit pattern of the exothermal metal passage is simultaneously transferred to the bottom of the copper base plate.
In the “Plating step”, a gold layer and a nickel layer are sequentially plated onto the circuit pattern of the connection pads.
Optionally, in the “plating step”, a nickel layer, a palladium layer and a gold layer are sequentially plated onto the circuit pattern of the connection pads.
Other objectives, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


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patent: 4953005 (1990-08-01), Carlson et al.
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patent: 5489059 (1996-02-01), Rostoker et al
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patent: 5905299 (1999-05-01), Lacap
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patent: 6087204 (2000-07-01), Fogelson
patent: 6091157 (2000-07-01), Black et al.
patent: 6093584 (2000-07-01), Fjelstad
patent: 554893-A2 (1993-08-01), None
patent: 361247060-A (1986-11-01), None
N/A, “Low Profile, Pseudo Wafer, Multi-chip Package.” IBM Technical Disclosure Bulletin, vol. 34, issue No. 3, pp. 145-147, Aug. 1, 1991.

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