Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-07-23
2001-05-15
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S701000
Reexamination Certificate
active
06232203
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of semiconductor manufacture, in particular to the problem of oxide loss and parasitic current leakage at the upper corners of isolation trenches in substrates.
BACKGROUND OF THE INVENTION
In semiconductor manufacturing, as submicron device size has become increasingly common, Shallow Trench Isolation (STI), because of the greater density of devices that can be placed on a substrate and improved planarity, has proven superior to the Local Oxidation of Silicon (LOCOS) technology. However, one problem that exists with STI is the loss of oxide at the top inside corners of the isolation trenches, ultimately resulting in parasitic current leakage for the active devices disposed on the substrate.
One prior art method for solving the “corners” effect at the trench edge is taught by Fazan et al (U.S. Pat. Nos. 5,433,794; 5,733,383) whereby an isolating material extends over the edges of the trench. Referring to
FIG. 1
, an insulating layer
5
has been deposited over a semiconductor substrate
1
on which has been deposited a pad oxide layer
2
and which contains a trench lined with a thermal oxide
2
a
and filled with an isolating material
4
. The spacers
5
shown in
FIG. 2
result after a dry etching process, the spacers being located at the corners of the trench and having similar chemical properties to the isolation material
4
. Referring to
FIG. 3
, a wet pad oxide etch causes the isolating material
4
to combine with the spacers
5
to form the cap
4
a
, which extends beyond the edges of the trench.
Certain other patents also address the subject of leakage at the upper corners of isolation trenches. For instance, Pan et al (U.S. Pat. Nos. 5,834,358; 5,763,932) teaches STI planarization processes using an etch back; Tseng (U.S. Pat. No. 5,801,082) planarizes an STI oxide using spin-on glass (SOG) spacers and an etch back; Abiko (U.S. Pat. No. 5,677,233) shows an STI planarization process that reduces oxide loss at trench corners using an oxide spacer; and Lee et al (U.S. Pat. No. 5,229,316) describes a process for forming an STI using a planarizing etch of a sacrificial layer. However, all of the etchback approaches from the prior art involve some kind of oxide deposition, either through chemical vapor deposition or spin-on, which adds to the complexity of the process. Moreover, oxide etchback processes will inevitably expose the substrate in the plasma, which can degrade the quality of the silicon substrate for subsequent device formation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a process for shallow trench isolation.
A further object of the invention is to prevent oxide loss on the top corners of the trenches, and the parasitic current leakage of the active devices resulting therefrom, that is caused by multiple wet etch/cleaning steps in the manufacturing process.
These objects have been achieved by forming shallow trenches having either stepped or tapered side walls in a silicon substrate using a pad oxide and silicon nitride mask. The dielectric material used to fill the trenches is then etched to form nitride spacers, which protect the top corners of the trench walls from subsequent etching but are removed prior to cleaning of the pad oxide and forming of gate oxide around the trenches.
REFERENCES:
patent: 4374011 (1983-02-01), Vora et al.
patent: 4389294 (1983-06-01), Anantha et al.
patent: 5229316 (1993-07-01), Lee et al.
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5677233 (1997-10-01), Abiko
patent: 5733383 (1998-03-01), Fazan et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5763932 (1998-06-01), Pan et al.
patent: 5801082 (1998-09-01), Tseng
patent: 5834358 (1998-11-01), Pan et al.
patent: 6033968 (2000-03-01), Sung
patent: 6040232 (2000-03-01), Gau
patent: 6063694 (2000-03-01), Togo
patent: 6080628 (2000-06-01), Cherng
Ackerman Stephen B.
Chaudhuri Olik
Duy Mai Anh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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