Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-10-21
2001-05-15
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185240, C365S185280
Reexamination Certificate
active
06233175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to the art of programming microelectronic flash Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method of programming microelectronic flash Electrically Erasable Programmable Read-Only Memory devices that provides self-limiting multi-level programming states.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to erase all of the cells as a block, to read the cell, to verify that the cell is erased or to verify that the cell is not overerased.
The memory cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of all the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is read by applying typically 5 volts to the wordline to which the control gate of the cell is connected, applying 1 volt to the bitline to which the drain of the cell is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. These applied voltages cause the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. In another arrangement, applying a negative voltage on the order of −10 volts to the control gate, applying 5 volts to the source and allowing the drain to float also erases a cell. A further method of erasing a cell is by applying 5V to the P-well and −10 V to the control gate while allowing the source/drain to float.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the source causing hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the respective programming voltages, the injected electrons are trapped in the floating gate creating a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
Attempts have been made to selectively program cells having different threshold voltages. However, because of manufacturing tolerances cells can have different threshold voltages when programmed. Because of this, tight control of the programmed states is difficult to achieve.
Therefore, what is needed is a method of self-limiting multi-level programming states of microelectronic flash Electrically Erasable Programmable Read-Only Memory devices that provides tightly controlled different programmed V
t
's.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of programming a flash EEPROM device to have multi-level programmed states.
In accordance with one aspect of the invention, a threshold voltage is selected for each cell and during programming a bias voltage is applied to the source of the cell to be programmed. The amount of the source bias voltage determines the level of the threshold voltage. The lateral field E
l
=V
d
−V
s
is adjusted to maintain the same during each of the programming steps.
In accordance with another aspect of the invention, the different source bias voltages are determined so that the programming is self-limiting by the effective vertical field E
v
=V
g
−V
t
−V
s
wherein V
t
increases during programming until the programming stops.
In accordance with still another aspect of the invention, a threshold voltage is selected for each cell and during programming a bias voltage is applied to the substrate of the cell to be programmed. The amount of the substrate bias voltage determines the level of the threshold voltage. The lateral field E
l
=V
c
−V
sub
is adjusted to remain the same during each of the programming steps.
In accordance with still another aspect of the invention, the different substrate bias voltages are determined so that the programming is self-limiting by the effective vertical field E
v
=V
g
−V
t
−V
sub
(V
s
=0), wherein V
t
increases during programming until the programming stops.
In accordance with still another aspect of the invention, a threshold voltage is selected for each cell and during programming a bias voltage is applied to both the substrate of the cell to be programmed. The amount of the substrate bias voltage and source bias voltages determines the level of the threshold voltage. The lateral field E
l
=V
c
−V
sub
−V
s
is adjusted to remain the same during each of the programming steps.
In accordance with still another aspect of the invention, the different substrate bias voltages and source bias voltages are determined so that the programming is self-limiting by the effective vertical field E
v
=V
g
−V
t
−V
sub
−V
s
, wherein V
t
increases during programming until the programming stops.
The described method thus provides self-limiting multi-level programming states in a flash EEPROM device.
REFERENCES:
patent: 5477485 (1995-12-01), Bergemont et al.
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5757699 (1998-05-01), Takeshima et al.
patent: 6097639 (2000-08-01), Choi et al.
Sunkavalli Ravi
Wang Janet
Advanced Micro Devices , Inc.
Mai Son
Nelson H. Donald
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