Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1997-12-01
2001-05-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S437000, C326S081000
Reexamination Certificate
active
06229365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a structure of a signal input/output unit providing an interface between this semiconductor integrated circuit device and an external device. More particularly, the present invention relates to a structure of a signal (including data signal) input/output unit of a synchronous semiconductor memory device that operates in synchronization with a clock signal.
2. Description of the Background Art
FIG. 15
schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to
FIG. 15
, a synchronous semiconductor memory device
1
includes an input circuit
2
operating with a power supply voltage Vddi applied to a power supply node
1
a
or a power supply voltage Vdd from a power supply node
1
d
and a ground voltage Vss as both operating power supply voltages for taking in an externally applied input signal IN at an input node
1
c
in synchronization with a clock signal CLK applied from a clock input node
1
b,
to generate an internal signal of a power supply voltage Vdd level, a memory internal circuit
3
operating with a power supply voltage Vdd applied to power supply node
1
d
and ground voltage Vss applied to a ground node
1
e
as both operating power supply voltages for carrying out a memory cell select operation and data writing/reading operation according to a signal applied from input signal
2
in synchronization with clock signal CLK, and an output circuit
4
operating with a power supply voltage VddQ applied to a power supply node
1
f
and a ground voltage VssQ applied to a ground node
11
as both operating power supply voltages for providing memory cell data read out from memory internal circuit
3
to a data output node
1
h.
Power supply voltage Vddi is at a level according to the power supply voltage level of the system in which synchronous semiconductor memory device
1
is employed. For example, power supply voltage Vddi takes the level of 2.5V or 1.8V. Power supply voltage Vdd is the power supply voltage used for the internal operation of synchronous semiconductor memory device
1
. Power supply voltage Vdd is higher than power supply voltage Vddi, and is, for example, 3.3V. By using power supply voltage Vddi as one operating power supply voltage in input circuit
2
, the input logic level of the memory device is adapted to the interface of a separate logic or processor and to the power supply voltage level of the system in which this synchronous semiconductor memory device is employed.
Input signal IN applied to input circuit
2
includes an address signal, a control signal, and write data. Memory internal circuit
3
includes a memory cell array with a plurality of memory cells, and a data write circuit and data read out circuit performing data writing and reading in synchronization with a clock signal.
Power supply voltage VddQ and ground voltage VssQ dedicated for output are applied to output circuit
4
. Output node
1
h
has a width of a plurality of bits such as 16 bits to allow many output buffers in output circuit
4
to operate simultaneously due to the dedicated voltages VddQ and VssQ. Output circuit
4
has to drive a large output load. This large output load must be driven at a high speed. By applying power supply voltage VddQ and ground voltage VssQ exclusively for data output, output circuit
4
can be operated stably. Also, the adverse effect of the power supply noise during operation of output circuit
4
on the operation of other circuits can be prevented.
Input circuit
2
receives a voltage Vddi according to the system power supply voltage as one operating power supply voltage to the first stage thereof connected to input node
1
c,
and takes in a signal according to this external interface to alter the voltage level for generating an internal signal of a power supply voltage Vdd level.
Ground voltage Vss to input circuit
2
may be applied via a node dedicated to the input circuit or via ground node
1
e.
FIG. 16
shows an example of a structure of the first stage of input circuit
2
of FIG.
15
. Referring to
FIG. 16
, the first stage of the input circuit includes a buffer circuit
2
a
operating with power supply voltage Vddi as one operating power supply voltage, and rendered operative when a first input stage cut signal ZNC generated from internal circuitry not shown is inactive (H level:logical high) for buffering an externally applied input signal IN for transmission to a node A, an inverter circuit
2
b
operating with power supply voltage Vddi as one operating power supply voltage for inverting the signal transmitted to node A from buffer circuit
2
a,
a level converter
2
c
for converting the amplitude of a signal applied to a node B from inverter circuit
2
b
to a level of power supply voltage Vdd, and an inverter buffer
2
d
operating with power supply voltage Vdd as one operating power supply voltage for buffering a level converted signal output from level converter
2
c
to generate an internal signal INT onto a node E.
First input stage cut signal ZNC applied to buffer circuit
2
a
is generated according to, for example, a chip select signal and a clock signal CLK. When first input state cut signal ZNC attains an active state of an L level (logical low), the synchronous semiconductor memory device attains a stand-by state. Therefore, no access is effected.
Buffer circuit
2
a
includes a p channel MOS transistor
2
aa
connected between a power supply voltage Vddi supply node Vddi (the node and the power supply voltage applied thereto are indicated by the same reference character hereinafter) and node A, and receiving first input stage cut signal ZNC at its gate, a p channel MOS transistor
2
ab
connected between power supply node Vddi and node A, and receiving an input signal IN
1
at its gate, and n channel MOS transistors
2
ac
and
2
ad
connected in series between node A and a ground voltage Vss supply node (referred to as ground node Vss hereinafter). First input stage cut signal ZNC is applied to the gate of MOS transistor
2
ac.
Input signal IN
1
is applied to the gate of MOS transistor
2
ad.
Inverter circuit
2
b
includes a p channel MOS transistor
2
ba
connected between power supply node Vddi and node B, and having a gate connected to node A, and an n channel MOS transistor
2
bb
connected between node B and the ground node, and having a gate connected to node A. Inverter circuit
2
b
has a structure of a CMOS inverter.
Level converter
2
c
includes a p channel MOS transistor
2
cc
connected between power supply node Vdd to which power supply voltage Vdd is supplied and a node C, and having a gate connected to a node D, a p channel MOS transistor
2
cd
connected between power supply node Vdd and node D, and having a gate connected to node C, an n channel MOS transistor
2
ca
connected between node C and the ground node, and having a gate connected to node B, and an n channel MOS transistor
2
cd
connected between node D and the ground node, and having a gate connected to node A. This level converter
2
c
has a structure of a shift latch type level converter.
Inverter buffer
2
d
includes a p channel MOS transistor
2
da
connected between power supply node Vdd and a node E, and having a gate connected to node C, and an n channel MOS transistor
2
db
connected between node E and the ground node, and having a gate connected to node C. Internal signal INT on node E is incorporated into the input circuit shown in
FIG. 15
in synchronization with clock signal CLK. Internal signal INT is also used for the internal operation.
The operation of the first stage of the input circuit of
FIG. 16
will be described hereinafter with reference to the operation waveform shown in FIG.
17
.
Before time t
0
, first input stage cut signal ZNC is at an active state of an L level. In buffer circuit
2
a,
MOS transistors
2
aa
and
2
ac
is in a conductive state and a non-conductive state, respectively. Theref
Iketani Masayuki
Ohbayashi Shigeki
Cunningham Terry D.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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