Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1997-03-13
2001-02-27
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S017000, C707S793000, C712S025000
Reexamination Certificate
active
06195628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention provides a system and method for circuit simulation. More particularly, it relates to a system and method for correct manipulation of waveforms in parallel time-warp simulations.
2. Background Art
The VHDL language is described in IEEE Standard VHDL Language Reference Manual, IEEE 1987. (VHDL refers to the VHSIC Hardware Description Language of IEEE standard 1076, where VHSIC means “very high speed integrated circuit.”) The concept of time warp has been described by Jefferson. See, D. R. Jefferson, “Virtual time,” in
ACM Transactions on Programming Languages and Systems,
pp. 404-425, July 1985.
During time-warp simulation of VHDL models it is possible that a simulation of an event on any processor (sometimes referred to as dispatcher) will schedule one or more transactions with simulation time less than the simulation time of already scheduled transactions (due to a simulation of previous events on processor's inputs) on an output of the processor. Such transactions will cancel one or more of the already scheduled transactions. This may happen because (i) of non-uniform propagation delays from the inputs of a logical process (also referred to simply as process) to its outputs and (ii) of the inertial delay model for the output. However, in time-warp simulation, the event generating new transactions, which canceled already scheduled transactions on the output, can get rolled back at some later time. In such a case we need to restore all the transactions which were canceled by the simulation of the rolled back event. Briner has proposed a solution for such event cancellation due to non-uniform propagation delay in switch-level time warp simulation of digital circuits which are not modeled in VHDL. See J. V. Briner, “Parallel Mixed-Level Simulation of Digital Circuits Using Virtual Time,” Ph.D. thesis, Duke University, 1990. However, Briner's solution does not deal with the complexities of multiple waveform elements for an output and/or transaction cancellation due to inertial delay model.
Consequently, it is an object of the invention to provide a system and method for handling transaction cancellation, particularly for waveform elements.
It is a further object of the invention to provide a system and method for handling transaction cancellation due to the inertial delay model in time-warp simulation of circuits modeled in VHDL or any other such HDL, e.g., Verilog.
It is a further object of the invention to provide a parallel VHDL simulation method which will run on any number of parallel platforms, including a cluster of workstations such as a cluster of IBM RS/6000 systems interconnected with a switch, such as the Allnode switch described in U.S. Pat. No. 5,404,461, the teachings of which are incorporated herein by reference.
SUMMARY OF THE INVENTION
In accordance with this invention, a system and method is provided for forward simulation and rollback during time warp simulation of events by organizing waveforms for each output of a processor by the simulation time (ST) of the events which created them and by the simulation time (RT) at which they are to be effective.
REFERENCES:
patent: 4899273 (1990-02-01), Omoda et al.
patent: 4901260 (1990-02-01), Lubachevsky
patent: 4985860 (1991-01-01), Vlach
patent: 5068812 (1991-11-01), Schaefer et al.
patent: 5091872 (1992-02-01), Agrawal
patent: 5157620 (1992-10-01), Shaar
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5272651 (1993-12-01), Bush et al.
patent: 5295065 (1994-03-01), Chapman et al.
patent: 5384720 (1995-01-01), Ku et al.
patent: 5418735 (1995-05-01), Saitoh
patent: 5442772 (1995-08-01), Childs et al.
patent: 5617561 (1997-04-01), Blaauw et al.
patent: 5649164 (1997-07-01), Childs et al.
patent: 5650946 (1997-07-01), Trimberger
patent: 5794005 (1998-08-01), Steinman
patent: 5801938 (1998-09-01), Kalantery
patent: 5832272 (1998-11-01), Kalantery
patent: 5956261 (1999-09-01), Blaauw et al.
J. V. Briner, Parallel Mixed-Level Simulation of Digital Circuits Using Virtual Time, Ph.D. Thesis, Duke University, 1990.
D. R. Jefferson, “Virtual Time”, inACM Transactions on Programming Languages and Systems, vol. 7, No. 3, Jul. 1985, pp. 404-425.
J. V. Briner, Parallel Mixed-Level Simulation of Digital Circuits Using Virtual Time, Ph.D. Thesis, Duke University, 1990.
http://www.opampbooks.com/ELE-VHLD/14.html, p. 1.
Y Lin and E. D. Lazowska, “Determining the Global Virtual Time in a Distributed Simulation”, in 1990International Confernce on Parallel Processing, pp. III-201 to III-209.
P. Heidelberger, et al. “Parallel Simulation of Continuous Time Markov Chains Using Uniformization with Adaptive Rates. ”IBM Technical Disclosure Bulletin, vol. 36, No. 7, Jul. 1993, pp. 15-17.
P. Heidelberger, et al. “Parallel Simulation of Continuous Time Markov Chains Using Uniformization with Adaptive Rates. ”IBM Technical Disclosure Bulletin, vol. 36, No. 7, Jul. 1993, pp. 15-17.
J. S. Steinman, “Synchronous Parallel System for Emulation and Discrete Event Simulation”, CC No. US 7880211, Dialog File 351: Derwent WPI, Sep. 15, 1992, p. 1.
“What is Vast?”,http://www.mtl.com/projects/vast/vaspage2.html, pp. 1-2.
Blaauw David T.
Radia Nimish S.
Skovira Joseph F.
Beckstrand Shelley M
International Business Machines - Corporation
Phan Thai
Teska Kevin J.
LandOfFree
Waveform manipulation in time warp simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Waveform manipulation in time warp simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Waveform manipulation in time warp simulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2560883