Electricity: power supply or regulation systems – Input level responsive
Reexamination Certificate
1999-06-22
2001-02-06
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Input level responsive
C323S303000
Reexamination Certificate
active
06184668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to voltage sensing in an integrated circuit, and more specifically, to a high-voltage sensor that prevents a low-voltage from being inadvertently sensed as a high-voltage during power-up and power-down and triggering an unintentional operation.
2. Background of the Related Art
Many integrated circuits require high-voltage sensor circuitry to detect higher than power supply (V
CC
) voltage levels in order to carry out operations such as read/write and erase. For example, on a flash memory EEPROM device, a low-voltage supplied to the device may indicate a read operation is to be performed, whereas a high-voltage (12V) supplied to the device (or internally generated via an on-board charge pump) may indicate a program operation or an erase operation is to be performed.
Therefore, in operation, high-voltage sensor circuitry detects the high-voltage, and in response, provides an output signal to other circuitry in the device to cause the device to enter a special operational mode (e.g., program, erase or test mode), other than a normal mode (e.g., read mode). If the high-voltage sensor does not operate properly, or inadvertently senses a low-voltage as a high-voltage, especially at power-up and power-down, a device such as a non-volatile memory may be erroneously programmed, erased, or stressed.
Normally, the output of a high-voltage sensor circuit provides a low voltage (V
SS
or GROUND). However, if the input to the circuit is greater than a predetermined voltage level, the output switches to a high-voltage (V
CC
, the power supply voltage). The switch to the high-voltage output occurs if the input voltage is greater than a specified reference voltage level higher than the power supply voltage V
CC
.
During the sequence of coupling the power supply voltage V
CC
to the integrated circuit (power-up), or of de-coupling the power supply voltage from the integrated circuit (power-down), many conventional high-voltage sensor circuits may furnish an output signal erroneously indicating that a high-voltage level has been applied to the device. Typically, these conventional high-voltage sensor circuits are designed to detect high-voltage input levels only during normal operation. Therefore, the conventional high-voltage sensor circuits require that the power-up sequence be followed exactly to ensure that the high-voltage sensor circuit does not erroneously furnish an output signal indicating detection of a high-voltage level.
One such conventional high-voltage sensing circuit is shown in FIG.
1
. As shown, the conventional high-voltage sensor
1
comprises a plurality of telescopically interconnected transistors
2
a-c
, which receive a voltage input, and in accordance therewith, provide a resultant output voltage. Additionally, the sensor
1
comprises a current source
3
and another transistor
4
.
Transistor
2
a
is connected at its source/drain terminal with the input signal VIN and its gate terminal is connected with the other source/drain terminal. Transistor
2
b
is connected at its source/drain terminal with the respective source/drain terminal of transistor
2
a
, while its gate terminal is connected with the other source/drain terminal. Therefore, a voltage threshold drop occurs across each of diode-connected transistors
2
a
and
2
b.
Transistor
2
c
has its source/drain terminal connected with the respective source/drain terminal of transistor
2
b
. The gate terminal of transistor
2
c
receives an input voltage source V
CC
. The other source/drain terminal of transistor
2
c
is connected with a current source
3
. The output VOUT of the circuit
1
is provided at node B. Finally, transistor
4
serves as a keeper transistor to keep the node A at a specific voltage range, such that node A does not float.
This conventional circuit suffers from the problems identified above with respect to inadvertent sensing of a low-voltage as a high-voltage during power-up or power-down because the threshold voltage of the gate terminal of FET
2
c
(which is connected with V
CC
) is still quite low. Thus, there is a need to provide an improved high-voltage sensing circuit that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage, primarily during power-up or power-down, and triggering a high-voltage operation such as a chip erase.
SUMMARY OF THE INVENTION
A high-voltage sensing circuit is provided that inhibits or prevents a low-voltage from being inadvertently sensed as a high-voltage and triggering a high-voltage operation such as a chip erase primarily during power-up or power-down.
The high-voltage sensing circuit comprises a high-voltage sensing circuit, a low-power sensing circuit, and a switch. The switch is controlled by the output signal of the low-power sensing circuit. Therefore, when the low-power sensor is activated, operation of the high-voltage sensing circuit is cut-off. When the low-power sensor is deactivated, i.e. the circuit has risen to a high-voltage status, then the high-voltage sensor is activated.
Thus, a low-voltage is prevented from being inadvertently sensed by the high-voltage sensing circuit as a high-voltage and triggering a high-voltage operation such as a chip erase.
REFERENCES:
patent: 4716307 (1987-12-01), Aoyama
patent: 5471130 (1995-11-01), Agiman
Nguyen Hung
Nojima Isao
Han Jessica
Limbach & Limbach LLP
Yin Ronald L.
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