Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-12-17
2001-12-25
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S262000
Reexamination Certificate
active
06333655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a duty deterioration preventing method thereof and particularly relates to a technique for preventing the deterioration of the duty of a propagating signal.
2. Description of the Related Art
The recent computerization or information-oriented trend is characterized by the increase of the quantity of information and higher transfer speed as can be seen from the transfer of images and voice through the Internet, the higher display resolution and the increase of use of mobile communications and the like.
For the purpose of downsizing, systems supporting the information-oriented society are required to be provided not only at low cost but also with high performance, which requirements are prominent for semiconductor integrated circuits serving as the center of the systems.
To realize high-speed, low-cost semiconductor integrated circuits, such measures are taken as one-chip mount, i.e., integrating and mounting a plurality of circuits on a single chip, and the reduction of the number of signal lines.
Accordingly, a circuit arrangement in which the number of signals is reduced by means of parallel/serial signal conversion (to be referred to as “P/S conversion”) and a Data-Strobe transfer method for generating a clock signal from a data signal and a strobe signal without using a clock signal to thereby transmit/receive signals at higher transfer speed, becomes a mainstream.
In the P/S conversion, it is essential to ensure timing accuracy of a clock signal relative to a serial signal, to reduce the difference between the rising time (tr) and the falling time (tf) of a serial signal, i.e., to make a duty ratio when the rate of change of a serial signal is the highest, closer to 50%.
Additionally, in case of the Data-Strobe transfer method, it is essential to reduce the skew of the data and strobe signals and to reduce the tr/tf difference between the data signal and the strobe signal so as not to deteriorate the duty ratio of a clock signal generated from the data and strobe signals, i.e., to make a duty ratio when either data or strobe signal operates in a cycle of a clock signal, closer to 50%.
The deterioration of the duty ratio derived from the tr/tf difference becomes prominent at high transfer speed. Considering this, too, it is a particularly demanded technique to make the duty ratio closer to 50% in recent years.
Next, a mechanism which causes the tr/tf difference to deteriorate a duty ratio will be described with reference to a circuit shown in
FIG. 1A and a
timing chart shown in FIG.
1
B.
Referring to
FIG. 1A
, this circuit is a variable delay circuit in which inverters are serially connected and the outputs of even stage inverters are connected to the next inverters and switch-added output blocks.
In this variable delay circuit, it is assumed that when a load is one inverter, a rising time tr
1
and a falling time tf1 satisfies the relationship of tr1=tf1, and when a load is an inverter and output block, a rising time tr2 and a falling time tf2 satisfies the relationship of tr2>tf2.
When a signal having a duty ratio of 50% is inputted to an input terminal, it is found that as the number of stages is increased, the distance between the rising edge and the falling edge tends to be narrowed and the duty ratio deteriorates in the circuit connection in which the even stage inverters have higher loads.
In order to meet the demand of preventing the deterioration of a duty ratio, for example, Japanese Patent Application Laid-Open (JP-A) No. 8-335861 has proposed a variable delay circuit having a circuit arrangement in which a plurality of identical inverters are serially connected and even stage inverters are connected to switch-added output blocks, respectively, characterized in that dummy load capacities (load circuits) are connected to the odd stage inverters (inverting buffers) and that the differences in driven capacity between odd stage inverters and the even stage inverters for the purpose of reducing the duty deterioration of output signals.
According to the technique disclosed in the above publication, as shown in
FIG. 2
, the capacities of the gates driven by the inverters are equal and duty deterioration derived form the difference in driven gate capacity is prevented. That is, the variable delay circuit
1
includes inverting buffers
3
1
, . . . ,
3
n
from the first to the n-th stages (where n is an even number) connected in series, switch circuits
5
1
, . . . ,
5
n/2
connected to output terminals b of the even numbered inverting buffers
3
2
,
3
4
, . . . ,
3
n
, respectively, an up/down counter circuit
7
for selecting one of the switch circuits
5
1
, . . . ,
5
n/2
and for outputting a signal I
1
from the selected switch circuit and load circuits
6
1
, . . . ,
6
n/2
connected to output terminals b of the odd numbered inverting buffers
3
1
,
3
3
, . . . ,
3
n−1
of the inverting buffers, and having equivalent loads to those of the switch circuits
5
1
, . . . ,
5
n/2
.
The circuit arrangement described in the above publication, however, has a problem that the difference in wiring capacity is generated depending on the difference in wiring length between blocks and the difference between adjacent wirings and crossed wirings and duty thereby deteriorates.
Furthermore, there are many cases where actual circuits, which functions are complicated and on which test modes are mounted, require an antangenient in which different blocks are mixed and circuit branches exist. With such a circuit arrangement, there is no avoiding the occurrence of the difference between a rising time (tr) and falling time (tf) depending on the combinations of driving capabilities and loads of the respective blocks. It is not, therefore, practical to prepare load adjustment blocks which satisfy all the combinations and to design a circuit.
Owing to this, it is difficult to prevent duty deterioration derived from wiring capacities even with a simple circuit in which identical blocks are serially connected, or particularly difficult with a circuit having different blocks and including branches.
This problem will be described in detail while taking the following cases as examples.
The first example, i.e., an example of a circuit arrangement in which identical circuit blocks (e.g., inverters) are serially connected, is shown in FIG.
3
A.
Duty deteriorates because of the difference in wiring capacity caused by the difference in wiring length among inverters and difference between crossed wirings and adjacent wirings.
The second example, i.e., an example of a circuit arrangement in which different circuits blocks (inverters and NAND circuits in this example) are serially connected, is shown in FIG.
3
B. Duty deteriorates because of the differences in driving capability and input capacity among circuit blocks as well as that in wiring capacity as in the case of the first example.
The third example, i.e., an example of a circuit arrangement having connection branches, is shown in FIG.
3
C. Duty deteriorates because of the difference in input capacity among circuit blocks and that in wiring capacity as in the case of the first example.
In an actually used semiconductor integrated circuit, the above-stated first to third examples are mixed, thereby making it more difficult to prevent duty deterioration.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit and a duty deterioration preventing method capable of preventing duty deterioration derived from the differences in wiring capacity, block driving capability and loads by using a simple circuit arrangement.
A method of preventing duty deterioration of a semiconductor integrated circuit according to the present invention is characterized in that the semiconductor integrated circuit includes a first circuit and a second circuit, which have the same combination of driving capability and driving capacity, and an inversion logic circuit in
Cox Cassandra
NEC Corporation
Sughrue & Mion, PLLC
Tran Toan
LandOfFree
Semiconductor integrated circuit and duty deterioration... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and duty deterioration..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and duty deterioration... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2560038