Method and system for making known good semiconductor dice

Details Method and system for making known good semiconductor dice Method and system for making known good semiconductor dice

1996-09-30

2001-07-10

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000, C438S017000, C324S755090, C324S765010, C324S537000

Reexamination Certificate

active

06258609

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to an improved method and system for making known good semiconductor dice by correcting defects in the dice during a testing procedure.
BACKGROUND OF THE INVENTION
Semiconductor dice must be tested during the manufacturing process to insure the reliability and performance characteristics of the integrated circuits on the dice. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dice. Standard tests for gross functionality are typically performed by probe testing the dice at the wafer level. Probe testing at the wafer level can also be used to rate the speed grades of the dice. Burn-in testing is typically performed after the dice have been packaged. During burn-in testing the packaged dice are subjected to elevated temperatures for extended periods of time while different electrical parameters of the integrated circuits are evaluated.
In addition to conventional plastic or ceramic semiconductor packages, semiconductor dice are also made in an unpackaged or bare form. A known good die (KGD) is a bare die that has been tested to insure a quality and reliability equal to a conventionally packaged product. For testing bare semiconductor dice, semiconductor manufacturers have developed specialized testing apparatus, such as carriers adapted to retain a single bare die for burn-in and other test procedures.
Bare dice that do not pass a test procedure are typically discarded by the manufacturer. Discarding defective dice decreases the yield of the known good die manufacturing process and adds to the expense of the dice. It would be advantageous to provide a test repair procedure that also increases the yield in the manufacture of known good dice.
SUMMARY OF THE INVENTION
In accordance with the invention, a method and system for making known good semiconductor dice are provided. The method, simply stated, comprises correcting defective dice during a testing process using programmable links formed on the dice. The programmable links comprise fuses or anti-fuses, in electrical communication with integrated circuits formed on the dice. Upon detection of a defect in a die, the programmable links on the die can be used to activate redundant integrated circuitry, or to program different operational modes to correct the defect. Following defect correction, rehabilitated dice can be tested and burned-in a second time, to insure their reliability as known good dice. Alternately, redundant circuitry on the dice can be constructed for test and burn-in during the initial testing process, such that a second test and burn-in are not required.
The system can include a testing apparatus adapted to simultaneously test multiple dice in singulated or wafer form. The testing apparatus includes, or is in electrical communication with testing circuitry and with programming circuitry. The testing circuitry is adapted to apply test signals to the dice to identify defects. The programming circuitry is adapted to apply programming signals to the programmable links to correct the defects.
For testing and repairing singulated dice, each die can be held in a temporary package and mounted to the testing apparatus. The temporary package can include a base for retaining the die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die against the interconnect.
To practice the method with singulated dice, semiconductor dice are fabricated or provided with programmable links and redundant, or programmable, integrated circuitry. The dice can be bare dice, bumped dice or chip scale packages. Following the fabrication process each die can be assembled in a temporary package for testing and defect correction. After assembly, the temporary packages can be placed on the testing apparatus, in electrical communication with the testing and programming circuitry. Initially, different tests including burn-in tests can be conducted to locate defects in the dice. With the dice still housed in the temporary packages, defects identified during testing can be corrected by selective actuation of the programmable links on the defective dice.
In an alternate embodiment, the singulated dice are not packaged in temporary packages. Rather, the testing apparatus is formed as a board adapted to retain multiple bare dice in electrical communication with testing and programming circuitry. Interconnects mounted to the board establish temporary electrical communication between the dice and the testing and programming circuitry. In addition, force applying mechanisms attachable to the board bias the dice against the interconnects.
In another alternate embodiment a wafer testing system is adapted to test and repair dice contained on a wafer. The system can include a wafer interconnect for establishing temporary electrical communication with each die contained on the wafer, and a force applying member for biasing the wafer against the wafer interconnect. The wafer interconnect can comprises a board configured to test one or more wafers or can be mounted in a housing configured to retain a single wafer.


REFERENCES:
patent: 4064493 (1977-12-01), Davis
patent: 4419747 (1983-12-01), Jordan
patent: 4899107 (1990-02-01), Corbett et al.
patent: 4918692 (1990-04-01), Hidaka et al.
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5106773 (1992-04-01), Chen et al.
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5119163 (1992-06-01), Ishihara et al.
patent: 5140554 (1992-08-01), Schreck et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5367253 (1994-11-01), Wood et al.
patent: 5387823 (1995-02-01), Ashizawa
patent: 5408190 (1995-04-01), Wood et al.
patent: 5424652 (1995-06-01), Hembree et al.
patent: 5440240 (1995-08-01), Wood et al.
patent: 5451165 (1995-09-01), Cearley-Cabbiness et al.
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495179 (1996-02-01), Wood et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5523697 (1996-06-01), Farnworth et al.
patent: 5530376 (1996-06-01), Lim et al.
patent: 5539324 (1996-07-01), Wood et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5578934 (1996-11-01), Wood et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5678301 (1997-10-01), Gochnour et al.
patent: 5764574 (1998-06-01), Nevill et al.
patent: 5768290 (1998-06-01), Akamatsu
patent: 5796264 (1998-08-01), Farnworth et al.
patent: 5815000 (1998-09-01), Farnworth et al.
patent: 5844418 (1998-12-01), Wood et al.

Affiliated with

Also associated with

Rating

Method and system for making known good semiconductor dice does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for making known good semiconductor dice, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for making known good semiconductor dice will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2559548