Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-08-29
2001-10-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C327S161000
Reexamination Certificate
active
06304511
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to control signal timing in semiconductor memory devices, and more particularly to a method and apparatus for selectively adjusting control signal timing in such memory devices.
BACKGROUND OF THE INVENTION
Semiconductor memory devices are used in a wide variety of applications. Such memory devices receive data for storage, in what is called a Write operation, and provide stored data to devices external to the memory, in what is called a Read operations. Typically, the memory device is accessed through a bus or multiple bus system by an external device or bus-master, such as a microprocessor, memory controller, or application specific integrated circuit (ASIC). The bus transfers address, data, and control signals between the memory device and the bus-master accessing the memory device.
Many of today's high speed memory devices, such as static random access memories (SRAMs), may operate at speeds greater than the capability of a bus-master accessing the SRAM. In a Read operation, for example, the SRAM may provide the data earlier than a time at which the bus-master is ready to retrieve such data. Bus contention may then result, in which data read from the SRAM is driven onto the bus while other data still resides on the bus. Consequently, two or more devices are sourcing/sinking relatively high currents for some conflicting period of time, thereby increasing risk of latchup effects, increasing system power consumption, increasing power and ground noise, and potentially resulting in erroneous data values.
To avoid such bus contention problems, designers of systems including high speed memories often insert idle time between successive data transfer operations, thereby reducing system speed to significantly less than optimal levels. Additionally, system designers often match speed specifications of various devices included within the system. As such, a system designer may not be able to use a readily available and inexpensive memory device in a system having other components too slow to match the speed of the memory device.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus is provided for selectively adjusting control signal timing in an integrated circuit, such as a memory device, that receives a clock signal and performs internal operations including producing a control signal. Clock sensing circuitry receives the clock signal and responsively produces a speed signal having a value corresponding to the frequency of the clock signal. Control signal delay circuitry receives the control signal and the speed signal, and responsively produces a delayed. control signal, with the time-delay relative to the control signal corresponding to the speed signal value.
The control signal may be any of a wide variety of control signals produced internal to a memory device and controlling the internal operations thereof. For example, the control signal may be a data output control signal controlling the timing of operations of data output circuitry included within the memory device. As another example, the control signal may be an address select control signal controlling the timing of access to an addressed location within the memory device.
The clock sensing circuitry may include a plurality of series-connected time-delay circuits, each able to receive a signal at its input and produce a corresponding time-delayed signal at its output. The clock signal is received at the input of a first of the time-delay circuits. The clock sensing circuitry may further include a plurality of latching circuits, each coupled with respective one of the time-delay circuits and latching the value of the respective time-delayed signal. The speed signal value may then correspond with the combination of latched values.
The control signal delay circuitry may include a plurality of time-delay circuits, each able to receive a signal at its input and produce a corresponding time-delay signal at its output with the control signal propagating through a selected number of these circuits. The control signal delay circuitry may further include delay select circuitry that receives the speed signal and correspondingly routes the memory control signal through a selected number of the time-delay circuits, with the selected number corresponding to the value of the speed signal.
By sensing the clock frequency and correspondingly adjusting control signal timing within the memory device, the speed of the memory device may be advantageously adjusted to match that of other components within the system. Among a number of advantages achieved in accordance with embodiments of the present invention, an SRAM device may be included within systems having operating speeds that would otherwise be too slow for the high speed access time of the SRAM device.
REFERENCES:
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patent: 5761151 (1998-06-01), Hatakeyama
patent: 5768177 (1998-06-01), Sakuragi
patent: 5841707 (1998-11-01), Cline et al.
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patent: 5986949 (1999-11-01), Toda
patent: 6111812 (2000-08-01), Gans et al.
Gans Dean
Pawlowski Joseph T.
Wilford John R.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Tan T.
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