Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-30
2001-02-20
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S244000, C327S293000
Reexamination Certificate
active
06191627
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit having adjustable delay units for clock signals.
U.S. Pat. No. 5,684,421 describes a delay locked loop (DLL) which generates a time-delayed output clock signal from an input clock signal. The output clock signal has a specific phase relationship with respect to the input clock signal. An adjustable delay unit is disposed between the input and the output of the DLL. The input and the output are additionally connected to a phase detector which controls the delay time of the delay unit as a function of the phase difference that is ascertained. It is also mentioned that a further adjustable delay unit can be provided in each case between the output of the DLL and/or the input of the DLL and the phase detector. Those further adjustable delay units serve for setting the phase angle of the output clock signal with respect to the input clock signal. The phase detector always determines the phase difference between the clock signals that are fed directly to it.
U.S. Pat. No. 5,684,421 also discloses a DLL having an input clock signal which is a differential clock signal that is fed to the delay unit through a line pair. The signals on both lines of the line pair are delayed uniformly by the delay unit. Consequently, the signals on both lines of the data line pair are delayed by the same delay time and fed to circuit components connected downstream of the DLL.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit having adjustable delay units for clock signals, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, in which two input clock signals are delayed, with the result that output clock signals being generated have a specific phase difference relative to a respective input clock signal, which is realized with little outlay and in which the output clock signals may each have different delays with respect to their input clock signals.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising a first delay unit having an adjustable delay time, an input for feeding in a first clock signal and an output; a second delay unit having an adjustable delay time, an input for feeding in a second clock signal and an output; a phase detector having a first input connected to the input of the first delay unit and a second input connected to the output of the first delay unit; a control unit controlling the delay time of the first delay unit for correcting, or controlling a deviation of, a phase difference ascertained by the phase detector and setting the delay time of the second delay unit to substantially the same value as that of the first delay unit; a circuit unit having a first input connected to the output of the first delay unit and a second input connected to the output of the second delay unit; and a third delay unit having an adjustable delay time, the third delay unit connected between the output of the second delay unit and the second input of the circuit unit.
In the case of the invention, the setting of the delay time of the first and second delay units is effected by the control unit as a function of the phase difference ascertained by the phase detector. The first delay unit is part of a control loop which is closed by the phase detector and the control unit. On the other hand, the delay time of the second delay unit is set only by the control unit to the same value as that of the first delay unit. Consequently, the output clock signal at the output of the second delay unit has the same time delay with respect to the input clock signal of the second delay unit as the output clock signal at the output of the first delay unit has with respect to the input clock signal of the first delay unit. However, according to the invention, the output clock signal of the second delay unit is not fed directly to the circuit unit to be controlled, but rather through the third delay unit. Since the delay time of the third delay unit is also adjustable, it is possible, through the latter, to set a desired phase angle of the output clock signal (fed to the circuit unit) of the second delay unit, independently of the delay time of the first delay unit.
In accordance with another feature of the invention, the second clock signal is the inverse of the first clock signal.
In accordance with a further feature of the invention, there is provided a fourth delay unit having an adjustable delay time, the fourth delay unit connected between the output of the first delay unit and both the second input of the phase detector and the first input of the circuit unit.
In accordance with an added feature of the invention, there is provided another or fifth delay unit having an adjustable delay time, the other or fifth delay unit connected between the second input of the phase detector and both the output of the first delay unit and the first input of the circuit unit.
In accordance with an additional feature of the invention, there is provided a further or sixth delay unit having an adjustable delay time, the further or sixth delay unit connected between the input of the first delay unit and the first input of the phase detector.
In accordance with yet another feature of the invention, signals with positive edges are present at the first and second inputs of the circuit unit, and the circuit unit has an output supplying an output clock signal having one edge type phase-locked with respect to the positive edges of the signal at the first input of the circuit unit and a second edge type phase-locked with respect to the positive edges of the signal at the second input of the circuit unit.
In accordance with a concomitant feature of the invention, the circuit unit is connected between the output of the first delay unit and the second input of the phase detector.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having adjustable delay units for clock signals, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Zweizig Jeffrey
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