Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-01-06
2001-10-09
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06301187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device operating in synchronism with an external clock signal.
2. Description of the Background Art
In accordance with improvements in the operating speed of recent microprocessors (hereinafter referred to as “MPUs”), synchronous type DRAMs (synchronous type Dynamic Random Access Memories, hereinafter referred to as “SDRAM”) or the like which operate in synchronism with a clock signal are used as a main storage device in order to implement high speed accessing.
In controlling internal operations of the SDRAM, the operations are divided into row-related operations and column related-operations.
Meanwhile, the SDRAM employs the bank configuration in which the memory cell array is divided into banks operable independently from each other. The operations are controlled independently for each bank for the row-related operations and the column-related operations.
In the SDRAM, the operation power supply voltage should be lowered for securing the reliability, as the transistor size tends to be even more reduced because of high density integration. With relatively low operation power supply voltage, the threshold voltage of transistors is generally lowered. Such lowering of the threshold voltage however gives rise to current leakage when the transistors are in the cut-off state as well.
Furthermore, as described above, in a multi-bank SDRAM, the control circuit requires a complicated configuration, which increases the number of circuits on the entire chip, and leakage current is likely to increase in stand-by operations or active operations.
The increase in the leakage current in the stand-by and active operations should be inevitably reduced, if a SDRAM is for example used in a portable instrument operating on a battery.
Problems Associated with Increasing the Number of Banks
In the SDRAM, 2 or 4 banks are generally used in order to achieve high speed operations.
Furthermore, in the Rambus SLDRAM, a configuration with a larger number of banks, 8 or 16 banks are requested.
If a memory circuit and a logic circuit are both mounted on the same chip, increase in the width of a data transmission bath increase in the bit number) within a chip is also requested.
A multi-bank DRAM is for example disclosed by Yoo et al. “A 32-bank 1 Gb Self-Storobing Synchronous DRAM with 1 Gbyte/s Bandwidth”, IEEE Journal of Solid-State Circuits, VOL. 31, No. 11, pp. 1635 to 1642, November 1996 (herein after referred to as “Conventional Art 1”.
FIG. 35
is a schematic diagram of the configuration of a memory cell array in a multi-bank DRAM
4000
according to Conventional Art 1.
Referring to
FIG. 35
, the memory cell array portion includes a memory cell array
4500
, a row decoder
4520
, and a column decoder
4530
. Memory cell array
4500
is divided into 8 banks along the direction orthogonal to the column direction, and the banks each include a sub array
4510
. Each sub array includes memory cells for storing data.
Multi-bank DRAM
4000
activates a bank including a memory cell selected in response to an address signal, and reads/writes data from/to the memory cell selected by row decoder
4520
and column decoder
4530
.
Meanwhile, memory cells having the same row address in memory cell array
4500
belong to the same bank, and are connected to one main word line. Thus, in a single row selecting operation, sense amplifiers corresponding to all the memory cells included in the same row should be activated, and this impedes reduction in the power consumption. Furthermore, a local column decoder is necessary for each of the banks, the area of a local column decode circuit band increases as the number of banks increases, and the chip area could be disadvantageously increased.
Conventional Art 2
In order to solve these disadvantages, Japanese Patent Laying-Open No. 9-73776 discloses a technique related to a multi-bank DRAM by which each bank is divided in the direction orthogonal to the row direction (hereinafter referred to as “Conventional Art 2”).
FIG. 36
is a schematic diagram of the configuration of a memory cell array portion of a multi-bank DRAM
5000
according to Conventional Art 2.
Referring to
FIG. 36
, the memory cell array portion includes a memory cell array
5500
, a row decoder
5520
, a word line driver
5525
, and a column decoder
5530
.
Memory cell array
5500
includes
4
banks formed by dividing the array in the column direction. Each of the banks is divided into sub arrays
5510
. Sub array
5510
includes a plurality of memory cells storing data.
In multi-bank DRAM
5000
, memory cells having the same column address are included in the same bank, and the banks include sub column decoders
5531
to
5534
. Thus, a column selecting line
5700
needs only be provided on a column basis.
FIG. 37
is a diagram of the arrangement of word lines in multi-bank DRAM
5000
.
Referring to
FIG. 37
, multi-bank DRAM
5000
includes a main word line
5710
provided for each row as a common signal line to all the banks, a sub word line
5720
for selecting a corresponding row in the same bank, and a logic gate
5730
for associating main word line
5710
and sub word line
5720
.
Main word line
5710
is connected with sub word line
5720
in each bank through logic gate
5730
. Logic gate
5730
is provided for each row in each bank, and receives main word line
5710
and selecting signals B
1
to B
4
. Logic gate
5730
takes the logical product of the main word line and a bank selecting signal to select a sub word line corresponding to main word line
5710
activated in the selected bank and starts a reading operation of data.
Thus, increase in the chip area by the area of the local column decoder band is restricted as much as possible, the sense amplifier band is divided on a bank basis and operates independently, and therefore the configuration is free from increase in the power consumption.
As the number of banks formed by dividing the array increases, the number of pieces of data which can be taken out from one bank is reduced, in other words, such a configuration is not suitable for multi-bit configurations.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous semiconductor memory device having a control circuit occupying a reduced area in the entire chip area by simplifying the configuration of the control circuit, if the storage capacity increases.
Another object of the present invention is to provide a synchronous semiconductor memory device such as SDRAM which permits reduction in current leakage in stand-by operations and active operations, if the storage capacity increases.
Yet another object of the present invention is to provide a synchronous semiconductor memory device which permits multi-bit data to be simultaneously input/output while restricting increase in the chip area or power consumption, if the number of banks is increased.
Shortly stated, a synchronous semiconductor memory device according to the present invention receives an address signal and a control signal, exchanges storage data and includes a memory cell array, an internal synchronizing signal generation circuit, an address signal input circuit, an address bus, and a plurality of selecting circuits.
The memory cell array has a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array is divided into a plurality of memory cell blocks. The internal synchronizing signal generation circuit outputs an internal dock signal in synchronism with an external clock signal. The address signal input circuit receives an external address signal in synchronism with the internal dock signal.
The address bus is provided commonly to a plurality of memory cell blocks, and transmits an address signal from the address signal input circuit.
The plurality of selecting circuits are provided for the memory cell blocks, and select a memory cell according to an address signal from the address bus. Th
Ooishi Tsukasa
Tomishima Shigeki
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tan T.
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