Static information storage and retrieval – Powering
Reexamination Certificate
2001-03-29
2001-12-04
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Powering
C365S227000, C365S189090, C365S189070, C365S210130
Reexamination Certificate
active
06327213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor memory device suitable to high integration, which stably operates with low power consumption. The present invention relates more specifically to a configuration of a power source for transmitting operating source voltages including a high voltage and a configuration of a voltage generating circuit.
2. Description of the Related Art
FIG. 71
is a diagram showing a configuration of an inverter which is a typical gate circuit. In
FIG. 71
, the inverter includes a p channel NOS (insulated gate type field effect) transistor PQ connected between a source node
1
and an output node
2
, and an n channel MOS transistor NQ connected between the output node
2
and a ground node
3
. An input node
4
is connected to the gates of the transistors PQ and NQ. The operation of the inverter shown in
FIG. 71
will now be described in brief.
When an input signal IN is high in level, the p channel MOS transistor PQ is turned off and the n channel MOS transistor NQ is turned on. The output node
2
is discharged to a ground potential level through the n channel MOS transistor NQ which is in an on state. When an output signal OUT at the output node
2
is lowered to the ground potential level, a source (corresponding to a conduction terminal connected to the ground node
3
) of the n channel MOS transistor NQ becomes equal in potential to a drain (corresponding to a conduction terminal electrically connected to the output node
2
) thereof. As a result, no current flows through the n channel MOS transistor NQ.
On the other hand, when the input signal IN is low in level, the n channel MOS transistor NQ is turned off and the p channel MOS transistor PQ is turned on. The output node
2
is charged to-a power source voltage Vcc level through the p channel MOS transistor PQ which is in an on state. When the output signal OUT at the output node
2
is raised to the power source voltage level, the source (corresponding to a conduction terminal connected to power source terminal
1
) of the p channel MOS transistor PQ becomes equal in potential to the drain (corresponding to a conduction terminal connected to the output node
2
) thereof, so that no current flows through the p channel MOS transistor PQ.
When the output signal OUT makes a transition to a high level or to a low level in the case of a CMOS (Complementary MOS) inverter using the p channel MOS transistor PQ and the n channel MOS transistor NQ, the transistors PQ and NQ are both brought into an off state eventually. As a result, no current consumption is produced in most Pasae. When the output signal OUT changes from the low level to the high level or vice versa, a through-current flows from the power source node
1
to the ground node
3
through the transistors PQ and NQ. Thus, the amount of current consumed can be reduced by using the inverter having the CMOS configuration shown in FIG.
71
.
A drain current Ids, which flows through an MOS transistor, is represented as a function of a gate-to-source voltage of the MOS transistor. As the absolute value of the gate-to-source voltage is made greater than that of a threshold voltage of the MOS transistor, the drain current increases. Even when the absolute value of the gate-to-source voltage is less than or equal to that of the threshold voltage, the drain current Ids is not completely brought to 0. The drain current that flows in a gate-to-source voltage region, is called “sub-threshold currents”, and is exponentially proportional to the gate-to-source voltage.
FIG. 72
is a graph showing a sub-threshold current characteristic of an n channel MOS transistor. In
FIG. 72
, the axis of abscissas represents a gate-to-source voltage Vgs and the axis of ordinates represents a logarithmic value of a drain current Ids. Linear regions of curves A and B shown in
FIG. 72
represent sub-threshold current regions. In the sub-threshold current regions, a gate-to-source voltage causing a drain current flow of 10 mA through a MOS transistor whose gate width (channel width) is 10 &mgr;m, for example, is defined as a threshold voltage. A threshold voltage Vth of a transistor having a sub-threshold current characteristic of the curve A is shown in FIG.
72
. As is seen from
FIG. 72
, a sub-threshold current It flows even when the gate-to-source voltage Vgs of the MOS transistor is 0V. When the number of MOS transistors used as components increases in a large scale integrated circuit device, the sum of values of sub-threshold currents attains a non-negligible, thereby causing a problem that the current consumption increases.
On the other hand, in a large scale integrated circuit device such as a large storage capacity semiconductor memory device or the like, an operating power source voltage Vcc tends to be set to a low voltage of 1.5V, for example, for the purpose of reducing power dessipation, speeding up its operation owing to a reduction in the amplitude of a signal and using a battery power. When the power source voltage Vcc is lowered, it is necessary to scale down a MOS transistor depending on the power source voltage in accordance with a scaling rule. When the MOS transistor is scaled down, it is also necessary to lower the threshold voltage Vth proportionally (when an n channel MOS transistor is used). However, the threshold voltage cannot be lowered in accordance with the scaling rule.
Namely, when the threshold voltage Vth of the MOS transistor having the sub-threshold current characteristic indicated by the curve A is reduced as shown in
FIG. 72
, the sub-threshold current characteristic represented by the curve A changes into that represented by the curve B. In this case, a problem arises that the sub-threshold current It when the gate-to-source voltage Vgs is 0V is increased to Ita, thereby causing an increase in consumed current.
Further, a high voltage Vpp greater than the operating source voltage Vcc is employed in a semiconductor memory device. By making use of the high voltage Vpp, the influence of a signal voltage loss produced by a threshold voltage of a MOS transistor is prevented and a signal having a power source voltage Vcc level is transmitted. Portions using such a high voltage Vpp will be described in detail later. However, a word driver for driving a word line into a selected state, for example, uses Vpp in the semiconductor memory device.
When the high voltage Vpp is used, the high voltage Vpp is applied in place of the source voltage Vcc in FIG.
71
. When the input signal IN is at a high voltage Vpp level, the p channel MOS transistor PQ is turned off. At this time, the n channel MOS transistor NQ is turned on and hence the output node
2
is discharged to the ground potential level. Since the high voltage Vpp is applied between the source and drain of the p channel MOS transistor PQ in this case, the voltage applied therebetween is made greater than the operating source voltage Vcc even if the gate-to-source voltage Vgs is 0V, whereby an electric charge is accelerated and more current flows so as to increase a sub-threshold current. Namely, the curve A shown in
FIG. 72
changes into the curve B thereby to increase the sub-threshold currents When the threshold voltage is determined, a drain voltage is set to a predetermined value. When the threshold voltage is reduced under the same drain voltage, the sub-threshold current increases. However, even if the MOS transistor has the same threshold voltage, if the drain voltage increases, then the curve A changes into the curve B.
The sub-threshold current characteristic of the p channel MOS transistor is represented by reversing the sign of the gate-to-source voltage Vgs of the curve shown in FIG.
72
.
In the circuit operating with the internal voltage such as the operating source voltage Vcc or the high voltage Vpp as described above, it is necessary to reduce a leakage current (sub-threshold current) of MOS transistor operating in the sub-threshold current region
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Viet Q.
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