Digital demodulator

Details Digital demodulator Digital demodulator

1998-06-11

2001-01-02

Lee, Benny (Department: 2817)

Demodulators

Phase shift keying or quadrature amplitude demodulator

C329S309000, C375S329000, C455S260000

Utility Patent

active

06169448

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a digital demodulator for demodulating signals which have been phase-modulated by such methods as PSK (Phase Shift Keying).
BACKGROUND OF THE INVENTION
In recent years, digital communication devices have transmitted information signals after modulating carrier signals using digital information signals (baseband signals) to achieve efficient transmission. Such modulation has been performed using methods such as ASK (Amplitude Shift Keying) in which amplitudes of carrier signals are shifted based on digital baseband signals (modulating signals), FSK (Frequency Shift Keying) in which frequencies of carrier waves are shifted based on modulating signals, and QAM (Quadrature Amplitude Modulation) in which amplitudes and phases of carrier waves are independently changed based on modulating signals.
These digital modulation methods are currently used in various mobile communication systems. Digital demodulators in practical use which demodulate information signals transmitted in the above manner have a common feature (not identical, though) in that a baseband signal is detected from an input signal using a clock signal which has a frequency equal to an integral multiple of the frequency of the input signal.
FIG. 1
is a block diagram of a digital demodulator of the prior art. This digital demodulator demodulates signals which have been phase-modulated by QPSK (Quaternary Phase Shift Keying). A radio signal inputted via an antenna is received by a radio unit (not shown) and then sent to a comparator
12
in a phase detector
11
as an input signal. A master clock signal has a frequency which is set at an integral multiple of the frequency of the input signal. The frequency of the master clock signal is divided by a divider
13
in the phase detector
11
and then compared with the frequency of the input signal by the comparator
12
, which outputs phase difference data. The frequency of the input signal is equal to that of the divided master clock signal.
The phase difference data outputted from the phase detector
11
is sent to a delaying circuit
14
, by which it is delayed by one information symbol period. The phase difference data is also sent directly to a subtractor
15
, which subtracts the delayed phase difference data from the original phase difference data. The subtraction result data is processed by a decision unit
17
, which then outputs demodulated data. The decision unit
17
operates based on an operation clock signal generated by a clock signal regenerator
16
, which generates operation clock signals in synchronization with the information symbol period.
FIG. 2
is a time chart of an unmodulated input signal (carrier wave) to be inputted to the digital demodulator and a divided master clock signal. The input signal is an unmodulated carrier signal, i.e., a carrier wave itself. A divided master clock signal is given by dividing the frequency of a master clock signal, which is an integral multiple of the frequency of the input signal. In this division, the frequency of the divided master clock signal is made equal to that of the input signal.
The phase difference between an input signal and a divided master clock signal is the constant value Pd. When an input signal is modulated, the phase difference Pd is shifted by the amount of modulation, and the modulated input signal can be demodulated based on the amount of shift.
However, when the frequency of a master clock signal is not an integral multiple of the frequency of an input signal, the input signal (carrier) is not in synchronization with the divided master clock signal, as shown in FIG.
3
. Here, the phase difference varies, as shown by PD
1
, PD
2
, PD
3
, and PD
4
. When an input signal is modulated, the amount of modulation is added to this varying phase difference so that it is difficult to demodulate the modulated input signal based on the phase difference as it is.
As shown in the above prior art, phase detectors of digital demodulators in practical use require each master clock signal to have a frequency which is an integral multiple of the frequency of each input signal.
With such configuration, however, an input signal needs to have a frequency which is an integral multiple of the frequency of a master clock signal, otherwise, the input signal can not be received.
This configuration also imposes restrictions on device design, since an oscillator needs to have a frequency which is an integral multiple of the frequency of an input signal to be demodulated.
To eliminate these problems, the present invention aims to provide a digital demodulator which imposes no restrictions on device design, regardless of the frequencies of input frequencies.
SUMMARY OF THE INVENTION
The digital demodulator of the present invention includes: a phase data output unit for comparing a phase-modulated input signal with a clock signal which is not in synchronization with the carrier wave of the input signal, and then outputting phase data which corresponds to the phase difference between the input signal and the clock signal; a delaying unit for delaying the phase data outputted from the phase data output means by a predetermined period of time; a compensation value hold unit for holding a compensation value which corresponds to the phase shift caused by the frequency difference between the carrier wave of the input signal and the clock signal; a delay detection unit for detecting the delay time of the phase data from the phase data output unit, using the phase data outputted from the phase data output unit, the compensation value held by the compensation value hold unit, and the phase data delayed by the delaying unit by the predetermined period of time; and a demodulation unit for demodulating the input signal based on the result of the delay time calculation.
In such digital demodulator, the delay detection unit is capable of calculating a delay time using the compensation value held by the compensation value hold unit, so that an input signal can be received and demodulated even if its frequency is not an integral multiple of the frequency of a master clock signal. Furthermore, an oscillator having a frequency which is not an integral multiple of the frequency of an input signal to be demodulated can be employed in this digital demodulator, allowing more freedom in device design, regardless of the frequencies of input signals.
The delay detection unit of such digital demodulator includes an addition unit for adding the phase data from the phase data output unit and the compensation value held by the compensation value hold unit, and a substraction unit for subtracting the phase data delayed by the delaying unit by the predetermined period of time from the addition result by the addition unit.
The installation of such addition unit and subtraction unit enables calculation of the delay time using the compensation value held by the compensation value hold unit.


REFERENCES:
patent: 5511097 (1996-04-01), Tsumura
patent: 464-814 (1992-01-01), None
patent: 2-230845 (1990-09-01), None
patent: 5-167631 (1993-07-01), None
patent: 5-191465 (1993-07-01), None
patent: 6-14070 (1994-01-01), None
patent: 6-30063 (1994-02-01), None

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