Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1997-03-27
2001-07-10
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S769000, C438S775000, C438S791000, C438S908000
Reexamination Certificate
active
06258690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a capacitor portion.
2. Description of the Prior Art
For semiconductor devices such as DRAMs, integration of a semiconductor device having a capacitor as a constituent element is progressing year by year.
For high integration, the wiring and circuit elements must be micropatterned. However, when the stored charge amount corresponding to a signal is reduced by micropatterning, an erroneous operation (software error) of the memory is caused by, e.g., radioactive rays such as &agr;-rays. To solve this problem, a technique of reducing the thickness of the dielectric film of the capacitor to increase the capacitance value of the memory is used.
In a semiconductor device manufacturing method disclosed in Japanese Unexamined Patent Publication No. 2-16763 (to be referred to as prior art
1
reference hereinafter), the polysilicon film surface of a lower electrode is nitrided to convert a spontaneous oxide film on the surface into a silicon nitride film. The silicon nitride film is grown by low-pressure chemical vapor deposition (to be referred to as LP-CVD hereinafter). With this technique, the growth of the spontaneous oxide film on the polysilicon film surface can be suppressed when the wafer is fed into the LP-CVD furnace, and a high capacitance value can be obtained.
FIGS. 1A
to
1
E are sectional views showing steps in manufacturing the semiconductor device of the prior art
1
reference. As shown in
FIG. 1A
, a silicon oxide film
2
is formed on a silicon substrate
1
, and a polysilicon film
9
as a lower electrode is deposited on the resultant structure. The polysilicon film is doped with an impurity such as phosphorus by ion implantation or diffusion. When the resultant structure is left to stand at room temperature, a spontaneous oxide film
10
is formed on the surface of the polysilicon film
9
, as shown in FIG.
1
B.
As shown in
FIG. 1C
, the spontaneous oxide film
10
formed on the surface of the polysilicon film
9
is converted into a silicon nitride film
11
by rapid thermal nitridation (to be referred to as RTN hereinafter).
As shown in
FIG. 1D
, a silicon nitride film
12
is deposited on the silicon nitride film
11
by LP-CVD. The surface of the silicon nitride film
12
is oxidized to form a silicon oxide film
13
. The dielectric film of a capacitor is constituted by the silicon nitride film
11
, the silicon nitride film
12
, and the silicon oxide film
13
. As shown in
FIG. 1E
, a polysilicon film
14
as an upper electrode is formed on the silicon oxide film
13
.
In a semiconductor device manufacturing method disclosed in Japanese Unexamined Patent Publication No. 5-190769 (to be referred to as prior art
2
reference hereinafter), an amorphous silicon film is formed on a polysilicon film as a lower electrode. After nitrogen atoms are ion-implanted, the amorphous silicon film is nitrided by RTN to form a silicon nitride film. With this technique, a high-quality thin dielectric film is realized.
FIGS. 2A
to
2
E are sectional views showing steps in manufacturing the semiconductor device of the prior art
2
reference. As shown in
FIG. 2A
, a silicon oxide film
2
is formed on a silicon substrate
1
, and a polysilicon film is deposited on the resultant structure. The polysilicon film is doped with an impurity such as phosphorus by ion implantation or diffusion and patterned into the shape of a lower electrode
3
. As shown in
FIG. 2B
, an amorphous silicon film
4
is formed on the surface of the polysilicon film by LP-CVD.
As shown in
FIG. 2C
, nitrogen atoms are implanted into the amorphous silicon film. As shown in
FIG. 2D
, the amorphous silicon film is nitrided by RTN and then oxidized to form a nitrooxide film
15
on the silicon nitride film. As shown in
FIG. 2E
, a polysilicon film is formed on the nitrooxide film
15
as a dielectric film. An impurity such as phosphorus is diffused, and the polysilicon film is patterned into the shape of an upper electrode
8
.
The above-described prior arts have the following problems.
In the prior art
1
reference, the silicon nitride film is formed on the polysilicon film as a lower electrode by RTN. However, no perfect silicon nitride film is formed on a silicon-oxide-based insulating film, i.e., the interlayer adjacent to the lower electrode.
In
FIGS. 1A
to
1
E, when the silicon nitride film
12
is to be formed by LP-CVD, the growth rate at the first stage of formation changes on the silicon nitride film
11
formed on the surface of the lower electrode
9
by RTN and on the silicon-oxide-based insulating film adjacent to the lower electrode. Since the thickness of the silicon nitride film
12
on the surface of the lower electrode is made different from that on the insulating interlayer, a leakage current easily flows.
FIG. 3
shows the relationship between the growth time and growth thickness of the silicon nitride film on the silicon nitride film and on the silicon-oxide-based insulating film. The growth is delayed on the interlayer, so a thickness difference of about 2.5 nm is generated for the same growth time.
As a result, the thickness of the silicon nitride film on the lower electrode
3
is made different from that on the silicon oxide film
2
as an interlayer, as shown in
FIG. 4
, resulting in a breakdown failure or leakage current.
More specifically, in
FIG. 4
, the lower electrode
3
is formed of the polysilicon film
9
shown in
FIGS. 1A
to
1
E, and the upper electrode
8
is formed of the polysilicon film
14
shown in FIG.
1
E. The surface of the silicon oxide film
2
serving as an interlayer or field insulating film is adjacent to the patterned lower electrode
3
. A dielectric film
16
in
FIG. 4
, i.e., the capacitive insulating film
16
of a capacitor is constituted by the silicon nitride film
11
, the silicon nitride film
12
, and the silicon oxide film
13
shown in
FIGS. 1D and 1E
. The most portion of this dielectric film
16
is constituted by the silicon nitride film
12
formed by CVD. That is, the thickness of the dielectric film
16
is dominantly determined on the basis of the thickness of the silicon nitride film
12
.
The spontaneous oxide film
10
formed on the surface of the lower electrode, i.e., the polysilicon film
9
can be converted into the silicon nitride film
11
by the process of RTN shown in
FIG. 1C
because the spontaneous oxide film
10
is very thin. However, no silicon nitride film is formed on the silicon oxide film
2
having the necessary thickness of an interlayer or field insulating film. More specifically, although the surface of the silicon oxide film
2
is nitrided, the resultant film contains much oxygen and therefore has a strong attribute as silicon oxide.
When the silicon nitride film
12
is to be formed by LP-CVD in the process shown in
FIG. 1C
, the growth thickness changes, as shown in FIG.
3
. As shown in
FIG. 4
, the dielectric film
16
formed on the surface (upper and side surfaces) of the lower electrode
3
becomes thick, and the dielectric film
16
formed on the silicon oxide film
2
becomes thin. For this reason, a constricted portion is formed in the silicon nitride film
12
at the lower end portion of the lower electrode
3
, i.e., a constricted portion
17
is formed in the dielectric film
16
.
In this state, a leakage current easily flows between the upper electrode
8
and the lower electrode
3
through this constricted portion
17
, and a breakdown failure easily occurs at this portion.
This problem arises for a capacitor for which the dielectric film
16
must be made thin, i.e., the silicon nitride film
12
must be made thin. If the design allows a thick silicon nitride film
12
, a sufficient thickness free from the problem of voltage in use can be ensured at any portion even when the thickness changes due to the delay in chemical vapor deposition.
To prevent the bre
Foley & Lardner
NEC Corporation
Thomas Toniae M.
Trinh Michael
LandOfFree
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