Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1997-10-06
2001-10-30
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S692000, C438S734000
Reexamination Certificate
active
06309947
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device with improved isolation region to active region topography.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution through the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, complimentary MOS (CMOS) transistors, bipolar transistors, bipolar CMOS (BiCMOS) transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions. In bipolar transistors, an active device generally includes a base, a collector, and an emitter.
Semiconductor devices, like the ones mentioned above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
One important step in the formation of semiconductors is the process of electrically isolating adjacent active devices. One known technique for isolating active devices on a semiconductor substrate is LOCOS (LOCal Oxidation of Silicon) isolation. LOCOS isolation generally involves the formation of a recessed or semi-recessed oxide
20
in the nonactive (or field) areas
22
of a substrate
24
which separate the active devices
26
, as illustrated in FIG.
1
A.
In one particular LOCOS process, a thin silicon dioxide layer, often referred to as a pad oxide layer is grown on the surface of a semiconductor substrate. A relatively thick layer of silicon nitride is then deposited over the pad oxide layer. Using a mask and etch process, the pad oxide
itride layers are then selectively removed to define active regions (generally those regions masked by the pad oxide
itride layers) and field regions (generally those regions over which the pad oxide
itride layers have been removed). The nitride layer acts as a mask during subsequent oxide growth. An oxide, typically referred to as a field oxide, is thermally grown in the field regions to a thickness ranging from 0.3 to 1.0 &mgr;m to electrically isolate the active regions. The pad oxide layer and nitride masking layer are then removed to expose the active regions of the substrate.
The structure resulting from LOCOS isolation techniques is typically associated with a number of limitations. One limitation in particular is the poor planarity of the resultant surface topography. This limits the maximum resolution of photolithography steps and serves to further impede scaling down of semiconductor devices.
One alternative to LOCOS isolation is trench isolation. A typical device utilizing trench isolation is illustrated in FIG.
1
B. Trench isolation generally involves covering the substrate
24
with a masking layer
27
which is then patterned and etched to expose one or more field regions
22
. Shallow trenches
28
are etched in the field regions
22
of the substrate
24
and the trenches
28
are refilled with a silicon dioxide layer
30
, which is etched back to form a relatively planar surface with masking layer
27
. The masking layer
27
is then removed. While trench isolation generally improves the planarity of the surface topography of the device, there is usually a height differential
32
between the source/drain regions
26
and the field regions
22
. The height differential
32
is approximately equal to the size of the masking layer
27
. Typical masking layer thicknesses range from about 1000-2000 angstroms or more. Reducing the size of the masking layer
27
, however, reduces its ability to protect the substrate below and may make the timing of the polishing process less flexible. A more detailed discussion of the LOCOS and trench isolation techniques as well as the advantages and disadvantages resulting therefrom can be found in S. Wolf,
Silicon Processing For The VLSI Era
, Vol. 2: Processing Integration, Chap. 2, pp. 12-66, 1990.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a method of manufacturing a semiconductor device with improved isolation region to active region topography. One embodiment is a method of making a semiconductor device. A masking layer is formed on a surface of a substrate. A portion of the masking layer is removed to define one or more field regions and at least one trench is formed in the field regions. An oxide layer is formed in the trench to substantially fill the trench. A portion of the oxide layer is removed to leave the oxide layer with a relatively planar surface that is recessed with respect to the masking layer. The masking layer is then removed to expose the substrate. A height differential may exist between the surface of the substrate surface and the relatively planar surface of the remaining portion of the oxide layer. The height differential, generally, is substantially less than the thickness of the masking layer.
In accordance with another embodiment of the invention, the oxide layer is removed in two stages. A first portion of the oxide layer is removed to form a surface of the oxide layer which is relatively planar with the masking layer. Subsequently, a second portion of the oxide layer is removed to leave a remaining portion of the oxide layer which has a relatively planar surface and is recessed with respect to the masking layer.
A further embodiment of the invention is another method of making a semiconductor device. A first masking layer is formed on a surface of a substrate. A portion of the first masking layer is selectively removed to define one or more field regions and one or more trenches are formed in the field regions. An oxide layer is formed which substantially fills the trenches. A second masking layer is then formed over the oxide layer and a portion of the second masking layer is selectively removed to expose a first portion of the oxide layer. The exposed first portion of the oxide layer is then removed, followed by the removal of the second masking layer. A second portion of the oxide layer is then removed to leave the oxide layer with a relatively planar surface that is recessed with respect to the first masking layer. The first masking layer is then removed to expose the substrate and leave a height differential between the substrate surface and the relatively planar surface of the remaining portion of the oxide layer. The height differential, generally, is substantially less than the thickness of the first masking layer.
Another embodiment of the invention is a semiconductor device which includes a substrate, one or more trenches in the substrate, and an oxide material substantially filling the trenches. The oxide layer has a relatively planar surface which extends less than about 500 angstroms above the substrate surface adjacent to the trenches.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The Figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 4666556 (1987-05-01), Fulton et al.
patent: 5229316
Bandyopadhyay Basab
Bonser Douglas J.
Advanced Micro Devices , Inc.
Fourson George
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