Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Utility Patent
1998-05-27
2001-01-02
An, Meng-Ai T. (Department: 2783)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C707S793000, C707S793000, C707S793000, C712S002000, C710S065000
Utility Patent
active
06170001
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the transferring of data between registers and memory in a data processing apparatus, and in particular to the transferring of such data in a data processing apparatus, wherein in a first mode of operation, data of a first data type consisting of an odd multiple of data words is processed, and in a second mode of operation, data of a second data type consisting of even number of data words is processed.
2. Description of the Prior Art
It is known to provide a data processing apparatus which can process data of different data types. For example, data of a first data type may consist of a first number of data words, whilst data of a second data type may consist of a second number of data words. For the purpose of the present invention, the term “data word” refers to a block of data having a predetermined number of data bits, but should not be construed as indicating any particular length. In preferred embodiments, a data word is a 32-bit block of data.
Hence, as an example, a data processing apparatus may be arranged in a first mode of operation to process single precision data consisting of a single data word, or in a second mode of operation, to process double precision data consisting of two data words. Alternatively, or in addition, other data types, such as triple or quadruple precision data, may be processed.
Prior to executing instructions on such data, it is usual for the data to first be loaded into a register bank. Separate register banks could be provided for each data type. Hence, as an example, single precision data would be stored in a single precision register bank, and double precision data would be stored in a double precision register bank. However, this approach may lead to the requirement for a large number of registers, thereby occupying a relatively large chip area.
In an alternative arrangement, a single register bank could be provided, with all data (irrespective of data type) being converted to a single internal representation prior to being stored in the register bank. Hence, considering the single and double precision example, each register in the register bank could be large enough to accommodate a double precision data value, and single precision data values could be expanded to a double precision format prior to being stored in the register bank. However, it will be appreciated that this approach can prove inefficient, since the internal representation needs to be large enough to accommodate data of the largest data type.
It is proposed to provide a single register bank for storing data of different data types, the register bank having a plurality of data slots for storing data words forming data of both a first data type (consisting of an odd multiple of data words) and a second data type (consisting of an even multiple of data words). By this approach, more efficient use of register bank space can be made. However, one problem occurs when the contents of the register bank need to be stored temporarily to memory, and then subsequently retrieved back into the register bank. When the data is loaded back into the register bank, the data processing apparatus may need to know whether any particular data word forms data of the first data type or data of the second data type. For example, this information may need to be available to subsequently executed processes. Further, if the internal format of the data (i.e. the format in the register bank) differs from the external format (i.e. the format in memory), and the differences depend on the data type, then the data processing apparatus needs to have access to the above information before the data can be reloaded into the register bank from memory.
Hence, it is an object of the present invention to alleviate the above identified problem in a data processing apparatus where a register bank may store data of different data types, data of a first data type consisting of odd multiples of data words, and data of a second data type consisting of an even multiple of data words.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a data processing apparatus, wherein in a first mode of operation, data of a first data type is processed, and in a second mode of operation, data of a second data type consisting of an even multiple of data words is processed, the data processing apparatus comprising: a register bank having a plurality of data slots for storing data words of data of said first type data and data words of data of said second type data; transfer logic, responsive to a store instruction, to control the storing of the data words in the register bank to a memory; a format register for storing format data indicating the distribution in the register bank of data words of data of said first data type and data words of data of said second data type; in said second mode, the transfer logic being responsive to said store instruction specifying an even number of data words to cause those data words to be stored from said register bank to said memory, and being responsive to said store instruction specifying an odd number of data words, to cause the format data from the format register to be stored to said memory along with an even number of data words from the register bank. In preferred embodiments, the data of the first data type consists of an odd multiple of data words.
In accordance with the present invention, a register bank is provided that has a plurality of data slots for storing data words, which may be data words of data of said first data type, or data words of data of said second data type. A format register is then provided for storing format data indicating the distribution in the register bank of data words of data of said first data type and said second data type. In situations where the data in the register bank needs to be temporarily stored to memory for subsequent retrieval into the register bank, for example in the event of a context switch event or as a result of procedure call entry and exit routines, then it becomes necessary to also store the format register to memory. However, this would typically require a further store instruction, which clearly has an impact on processing speed.
To avoid this problem, the present invention is arranged such that in said second mode, where data consisting of an even multiple of data words is processed, the transfer logic is responsive to the store instruction specifying an even number of data words to cause those data words to be stored from said register bank to said memory, and is responsive to said store instruction specifying an odd number of data words, to cause the format data from the format register to be stored to said memory along with an even number of data words from the register bank. Hence, in situations where the data in the register bank needs to be temporarily stored to memory for subsequent retrieval into the register bank, all that is required is for the store instruction to be issued in said second mode specifying an odd number of data words, and this will automatically cause the contents of the format register to be stored to memory in addition to the required even number of data words from the register bank.
Thus the present invention enables a single register bank to be used to store both data of a first data type and a second data type, and for information about the distribution of the data in the register bank to be selectively stored to memory as required, without increasing the number of instructions, and hence without adversely affecting processing speed during a store to memory or load from memory process.
If the code initiating the store instruction is aware of the register bank content, then there may be no need to store the format register contents to memory. However, in preferred embodiments, if the store instruction is initiated by code unaware of the register bank content, the store instruction is arranged to be issued in said second mode specifying an odd number of data words, upon receipt of the store instruction, s
Hinds Christopher N.
Seal David J.
An Meng-Ai T.
ARM Limited
El-Hady Nabil
Nixon & Vanderhye P.C.
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