Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-06-18
2001-01-16
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S437000, C148SDIG005
Reexamination Certificate
active
06174785
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices. More particularly, the present invention relates to a method of forming shallow trench isolation regions for a semiconductor device.
2. The Relevant Technology
Electronic devices such as field-effect transistors (FETs) are useful in fabricating integrated circuits such as those used in memory chips and microprocessors. The FETs used in high performance complementary metal oxide semiconductor (CMOS) circuits require advanced isolation techniques for filling recessed field oxide regions. One common isolation technique is known as local oxidation of silicon (LOCOS).
In the LOCOS technique, a thermal oxide liner is formed on a substrate, followed by an island of silicon nitride being formed thereover. The substrate is then placed in an oxidation steam ambient at a high temperature to oxidize the exposed silicon, with the silicon nitride forming a barrier to the steam ambient. The energetic hydrogen and oxygen ions in the steam ambient react with the exposed silicon at high temperature to form a glass which grows by consuming the silicon to form silicon dioxide.
While LOCOS is suitable for certain applications, it has some disadvantages. For example, the LOCOS process is often not suitable for deep submicron dimensions for density driven memory applications because it can result in an undesirable isolation encroachment into the active area of the device. This is commonly referred to in the industry as a “bird's beak.” One of the problems of the LOCOS technique is that when a device is scaled down to smaller geometries, it is harder to control the length of the bird's beak, resulting in a very high stress in the silicon leading to stress related defects such as undesirable current leakage.
In other conventional isolation techniques such as shallow trench isolation (STI), islands of nitride are formed and then a trench etch is done to trench the silicon around the islands of nitride. This results typically in a very abrupt-shaped trench. The trenches are subsequently filled with an oxide insulator material, and then polished back and isolated out. While the use of STI leads to many desirable circuit device properties, the technique also possesses some disadvantages. One significant drawback common in STI processes is the presence of “edge conduction,” which is excessive current leakage in the upper region between the top of a filled oxide trench and an adjacent silicon mesa. Devices which exhibit high edge conduction are characterized by significant parasitic leakage, which is very undesirable.
A method for forming trench-isolated FET devices to improve subthreshold leakage characteristics is disclosed in U.S. Pat. No. 5,643,822 to Furukawa et al. This method involves forming a vertical slot within a stack structure disposed on an oxide covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate, followed by removal of the spacers to uncover a horizontal ledge on the exposed surfaces of the substrate adjacent to the trench. The ledge is then perpendicularly implanted with a suitable dopant to suppress edge conduction in the device. This method results in an abrupt-shaped trench with sharp corners which can cause undesirable electrical characteristics in the trench. The sharp corners of the trench can also lead to difficulties in depositing the trench with a filler material during subsequent processing. The sharp corners can lead to pinching off the upper opening to the trench during deposition before the trench is filled, leaving an undesirable void in the trench.
Accordingly, there is a need for an improved semiconductor trench forming method that overcomes or avoids the above problems and difficulties.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming shallow trench isolation regions having novel trench configurations for a semiconductor device. The method of the invention utilizes sacrificial spacers having a rounded or curved shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate to define the profile of the trench. A trench with substantially rounded upper and lower corners is formed in the semiconductor substrate. The rounded shape for the trench improves and enhances the electrical characteristics of the trench, resulting in reduced current leakage. The rounded shape of the trench also provides a more optimized trench profile for filling the trench with a filler material during subsequent fabrication procedures.
In one aspect of the invention, a method of forming a trench isolation region is provided. The method includes providing a silicon substrate with a stack structure formed thereon comprising a layer of oxides of silicon. A vertical slot is formed in the stack structure from a patterned photoresist layer on the stack structure, with the slot having a first width between a pair of slot sidewalls. An overlying spacer layer such as polysilicon is then deposited over the stack structure and vertical slot. The spacer layer is etched to form curved spacers along the sidewalls of the slot. A trench is then etched in the substrate below the slot while simultaneously removing the spacers such that the shape of the spacers is transferred into the trench. The trench has a second width which is less than the first width of the slot. The trench has a pair of upper corners with a substantially rounded profile, such as a convex profile, adjacent to the sidewalls of the slot, and a pair of lower corners with a substantially concave profile.
In further processing steps, an oxide filler material is deposited in the trench and over the stack structure to form a covering layer. The covering layer and stack structure are then planarized so as to form a filled trench region which electrically isolates active areas in the substrate. The planarization can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching.
In another aspect of the invention, a trench isolation structure formed according to the above method is provided in a semiconductor device for electrically isolating active areas in the device. The trench isolation structure includes a semiconductor substrate having an upper surface, and a trench formed in the substrate. The trench is defined by a pair of sidewalls and a bottom wall that is substantially perpendicular to the sidewalls. The trench has a pair of upper corners with a substantially convex profile and a pair of lower corners with a substantially concave profile. The upper corners of the trench join the sidewalls of the trench with the upper surface of the substrate, and the lower corners of the trench join the sidewalls with the bottom wall of the trench. This results in trench configuration having a substantially rounded V-shaped or U-shaped profile. An oxide filler material is disposed in the trench and forms an upper cap structure over the trench which is above the upper surface of the substrate.
Other aspects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
REFERENCES:
patent: 4839306 (1989-06-01), Wakamatsu
patent: 5254218 (1993-10-01), Roberts et al.
patent: 5308784 (1994-05-01), Kim et al.
patent: 5360753 (1994-11-01), Park et al.
patent: 5612242 (1997-03-01), Hsu
patent: 5620930 (1997-04-01), Hey et al.
patent: 5640041 (1997-06-01), Lur et al.
patent: 5643809 (1997-07-01), Lien
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5661049 (1997-08-01), Lur et al.
patent: 5665632 (1997-09-01), Lur et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5753561 (1998-05-01), Lee et al.
patent: 5807789 (1998-09-01), Chen et al.
Li Li
Parekh Kunal R.
Dang Trung
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
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