Concurrent legacy and native code execution techniques

Data processing: structural design – modeling – simulation – and em – Emulation – Compatibility emulation

Reexamination Certificate

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Details

C712S200000, C703S027000

Reexamination Certificate

active

06272453

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for emulating legacy instructions of a microprocessor and more particularly to a method and apparatus which enables a legacy microprocessor to be upgraded with an upgrade microprocessor with an incompatible instruction set and execute both legacy and native code.
2. Description of the Prior Art
It is known that microprocessors are configured with different instruction set architectures (ISA). The ISA determines the instruction set for a particular microprocessor. Application programs are executed by the microprocessors normally written in relatively high level language, which is compiled into machine instructions compatible with the instruction set for the specific microprocessor. Microprocessors are increasingly being designed to execute instructions faster and faster. As such, systems incorporating such microprocessors are often upgraded to increase the speed of the system. Unfortunately, depending on the particular upgrade, often times the instruction set of the upgrade microprocessor is incompatible with the instruction set of the microprocessor to be replaced (“legacy microprocessor”). As such, in such applications, the existing application programs often need to be rewritten in new and modern computer languages with modern compilers. Unfortunately, such an undertaking can be quite cumbersome and expensive.
Due to the age and obsolescence of many existing avionic onboard computers, the reliability of such computers is rapidly declining while maintenance is becoming more difficult and costly to achieve. As such, it is sometimes required to replace outdated “legacy” microprocessors with newer technology microprocessors. To work around instructions set incompatibilities, emulation systems (emulators) have been developed. Emulators are known which emulate the instructions set of the legacy microprocessor in order to enable the instructions of the legacy microprocessor to be “executed” by a different microprocessor. Both software and hardware based emulators are known. For example, various software emulators for the F-16 avionics integration support facility (AISF) common modular environment (COMET) are described in document no. F-16AISF-COMET-100 (EMULATORS-SWD-A, dated May 21, 1996). Hardware based emulators for military standard MIL-STD-1750A, are discussed in the document entitled Line Replaceable Unit Emulator Hardware Product Fabrication Specification, document no. SFF20702 dated Apr. 16, 1996.
Unfortunately, known software emulators have been known to be relatively inefficient. In particular, in such known software emulators, legacy instructions are fetched for the upgrade microprocessor which uses a look up table to interpret the legacy instruction. Since each legacy instruction must be interpreted, computer systems which incorporate cache memory are known to suffer from relatively high probability of cache misses which decreases the overall throughput of the system.
Another problem with known software emulators is the inability to optimize the native code environment. Thus there is a need to improve emulation software routines which allows for optimizing of the native code environment.
SUMMARY OF THE INVENTION
Briefly, the present invention relates to a method and apparatus for emulating instructions of a microprocessor (“legacy instructions”) with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of “thunk” objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.


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