Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1998-12-22
2001-07-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S202000, C327S213000
Reexamination Certificate
active
06265922
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a controllable latch/register circuit, especially (but not exclusively) for implementation within an integrated circuit.
BACKGROUND OF THE INVENTION
Latches and registers are used commonly in many various types of integrated circuits for temporary storage of signals between circuit elements and for interfacing to external circuitry. Latches are transparent when open, and latch the data when closed. In contrast, registers have independent input and output buffers, to provide a stable output during loading of subsequent data. The register is never transparent, since the output buffer holds the previous outputs stable until the input buffer has closed, whereupon the data in the input buffer is transferred to the output buffer.
For reference, a known design of register circuit is described with reference to
FIGS. 1 and 2
. The register comprises an input (master) latch
10
coupled in series with an output (slave) latch
14
. The latches are controlled by a so-called “hat” cell
12
which generates control pulses to open each latch in turn to provide register operation. This is illustrated in the timing diagram of FIG.
2
. During a load enable cycle, the master latch is opened during first clock pulse
16
to admit input data into the master latch
10
. The master latch is transparent when open but, during the cycle
16
, the slave latch remains closed, thus keeping the original output stable. During the subsequent clock pulse
18
(while the enable signal is still active), the master latch
10
is closed to latch the data held in the master latch
10
, and the slave latch
12
is opened to admit the data through to the register output.
Registers typically are used for circuits in which a stable output is required throughout a processing cycle, and transparent operation is not desirable. In contrast, latches on their own are used in preference to registers for circuits which do not require a stable output through a processing cycle; such latches provide a considerable speed advantage in generating an output immediately on an enable signal loading the signal into the latch.
However, the use of independent latches does not provide full compatibility with register scan testing which is becoming an important technique for testing integrated circuits. Scan testing utilises a special scheme for shift-loading known test values into registers of an integrated circuit x, running the circuit for a controlled number of cycles (for example, only one cycle), and then shift-loading all of the result values from the registers. By comparing the actual result values with the correct theoretical values, the functionality of the circuit can be tested thoroughly. However, scan testing relies on shift-register operation to shift the data values serially into and out of the integrated circuit. Such register operation is not supported by independent latches because the latches become transparent when open. Although it is possible to read latched values separately (requiring the use of additional logic circuits and data paths), it is not normally possible to combine registers and latches in a single scan-test data path.
Circuits exhibiting both latch and register behaviour are known, for example, in certain core interface circuits capable of interfacing with either synchronous or asynchronous memory. Generally, a transparent latch is preferred for accessing synchronous memory, because the address and control signals are required only at a cycle edge, and the signals are interfaced more quickly with a latch. However, for asynchronous memory, stable signals are required throughout the cycle, requiring the use of an interface register.
An example of a conventional circuit for providing both latch and register behaviour is illustrated in FIG.
3
. The circuit consists of an edge triggered register
20
, and a bypass path
22
. The output from the register
20
and the bypass path are fed to a multiplexor
24
, which selects one of the signals for output depending on a “select” signal
26
which doubles as the “load enable” signal for the register
20
. When the register is enabled for loading (i.e. the output does not represent the signal being inputted), the multiplexor selects the bypass signal, to allow the signal directly through to the output (transparent latch behaviour). When the load enable signal is deactivated, the multiplexor selects the stable register output (register behaviour).
However, such a circuit is not ideal because the presence of the multiplexor requires additional chip space, and increases the circuit cost. Moreover, the circuit is not suitable as a universal latch/register because it may not provide precisely the same timing characteristics as a conventional latch or a conventional register. This complicates modelling of the circuit element to simulate operation of the overall circuit environment.
The present invention has been devised bearing the above problems in mind.
SUMMARY OF THE INVENTION
In one aspect, the invention provides a circuit operable as a register or as a latch, the circuit comprising a first latch coupled in series to a second latch, and a control circuit operable to control operation of the first and second latches in a first mode in which the latches are controllable to behave substantially as a single latch, and in a second mode in which the first and second latches are controllable to provide register operation.
With the invention, a circuit can be provided which is not significantly more complicated than a register, but which can be controlled to provide either fully compatible latch operation, or fully compatible register operation.
For example, in the first mode, one of the latches could be controlled to be open permanently, or at least for the majority of a cycle. When held open throughout a cycle, the latch is totally transparent (i.e. the output always equals the input, and so the presence of that latch has no effect on the signal). The circuit is thus be equivalent to a single latch (i.e. the remaining latch) which can be controlled in a conventional manner.
Preferably, the control circuit is operable in a plurality of different modes to hold one or the latches open, the other latch being controllable to respond differently, depending on the mode, to one or more external timing and/or control signals, for example, a clock signal and a load enable signal.
In one form, the latch/register circuit (also referred to herein as a “latchister”) may be used as a universal circuit for implementing latches and for implementing registers. The use of such a universal circuit can simplify cell design, and can provide standard timing, thus simplifying modelling of the circuit in a timing model.
In a preferred embodiment, the latchister is used as an interface circuit for providing a buffer to external memory, which may be synchronous or asynchronous memory. The latchister can be configured to provide optimum latch or register characteristics to suit the type of memory.
In another preferred embodiment, the latchister is used in a circuit to provide latching operation during normal operation of the circuit, but is coupled to other registers or latchisters to provide scan-test register operation during scan-testing. Such a technique is extremely important in enabling scan-testing of a circuit while still allowing the speed advantages of latches to be exploited when the circuit is in normal use.
REFERENCES:
patent: 4703257 (1987-10-01), Nishida et al.
patent: 4864161 (1989-09-01), Norman et al.
patent: 5317205 (1994-05-01), Sato
patent: 5321399 (1994-06-01), Notani et al.
patent: 5378934 (1995-01-01), Takahashi et al.
patent: 5416362 (1995-05-01), Byers et al.
patent: 5459736 (1995-10-01), Nakamura
patent: 5703513 (1997-12-01), Hashizume et al.
patent: 5945858 (1999-08-01), Sato
patent: 6005422 (1999-12-01), Morinaka et al.
patent: 6060924 (2000-05-01), Sugano
Callahan Timothy P.
LSI Logic Corporation
Luu An T.
Oppenheimer Wolff & Donnelly LLP
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