Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With microwave gas energizing means
Utility Patent
1998-02-24
2001-01-02
Gulakowski, Randy (Department: 1746)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With microwave gas energizing means
C451S285000, C451S287000
Utility Patent
active
06168683
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the surface treatment of workpieces and in particular to polishing and the like surface treatment operations performed on semiconductor wafers.
2. Description of the Related Art
High quality semiconductor wafers are used in the commercial production of integrated circuit devices, with each wafer ultimately being divided to provide a relatively large number of such devices. Repeated detailed processing is required during integrated circuit production. The inherent value of the semiconductor wafer blank is relatively high, and increases dramatically as additional operations are performed on it. One figure of merit for cost reduction of integrated circuit production is the number of integrated circuit devices that can be obtained from a particular semiconductor wafer. With the continued miniaturization of electronic components, the finished size of integrated circuit devices is becoming smaller.
Accordingly, as the number of circuits (or circuit density) on a semiconductor wafer increases, the spacing between adjacent electronic structures (e.g. conductive lines) is being dramatically reduced in size. It has been found convenient to operate on the semiconductor wafers in multiple stage mass operations, each stage developing a layer of circuitry throughout the entire wafer, in a single operation. Such operations typically employ photographic techniques. However, as the relative size of the electronic devices is reduced, the focus and depth of field of the imaging processes used for integrated circuit production becomes increasingly sensitive to surface variations on the semiconductor wafer substrate. This has increased the desire for semiconductor wafers with improved surfaces, especially surfaces having improved flatness. During the fabrication process, layers are added to, or incorporated in, the semiconductor wafer surface, with conductors and dielectric structures being built on top of underlying layers. It has been found necessary to restore the desired flatness of the resulting exposed surface after each such operation.
Restoring flatness of a semiconductor wafer (commonly referred to as “planarization”) is achieved using various wafer polishing techniques. Such polishing generally includes attaching one side of the semiconductor wafer to a flat reference surface of a wafer carrier or chuck, and pressing the exposed surface of the wafer against a flat polishing surface. During the polishing operation, both the polishing surface and the wafer surface may be rotated or made to undergo relative oscillation to further improve the polishing action. The polishing surface typically comprises a pad attached to a rigid flat table. A specially composed slurry having desired abrasive and/or chemical properties is introduced into the polishing process. The combined effects of the pad, the slurry and the relative movements of the wafer and polishing surface produce an enhanced chemical/mechanical treatment of the wafer surface.
One important objective of practical polishing operations for integrated circuit production is to reduce surface variations to a low level (e.g., less than 0.1 micron). Although substantial advances have been made over the years to allow the attainment of an extremely flat surface, precision processing has required attention to virtually every component of the overall process. For example, considerable attention has been paid to the production and post production enhancement of polishing pads which are relied upon to perform mechanical work on the semiconductor substrate surfaces and to carry the chemical and abrasive components of the slurry. It has been observed that spent particles developed during the polishing process become embedded within the polishing pad, changing its precisely controlled characteristics and requiring pad replacement on a relatively frequent basis. Accordingly, polishing pads are considered to be a consumable component of the polishing operation. However, the processing and post processing treatment of the polishing pads, in order to attain the precision surface properties necessary to impart the desired flatness to a semiconductor wafer, is achieved at a considerable cost. Recent industrial proposals have raised a likelihood of substantially increasing semiconductor wafer sizes from 8 inch to 12 inch diameter sizes. Considerable cost and technological differences have been encountered in the past when substantial increases in polish pad sizes have been proposed. Speed of wafer polishing, or in a production setting, wafer throughput, has always been of interest and lies behind the drive to overcome the substantial challenges presented with larger wafer sizes. Methods and apparatus to produce improved polishing, particularly rapid automated polishing of larger sized semiconductor wafers, is desired, and these needs are met by the present invention.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide apparatus and method for the automated polishing of semiconductor wafers and similar components.
Another object of the present invention is to provide apparatus and methods which are capable of flexible operation, where different modes of surface treatments can be provided on an ongoing, routine basis.
Another object of the present invention is to provide apparatus and methods for the surface treatment of wafers in which multiple individually controlled processes are performed on each wafer.
These and other objects of the present invention which will become apparent from studying the appended description and drawing are provided in an arrangement for polishing a surface of a semiconductor wafer, comprising:
a support structure;
a carrier table having a central axis and carried by the support structure for rotation about the central axis, the carrier table defining a plurality of wafer-receiving positions each having an upper, support surface for supporting the semiconductor wafer;
a plurality of polishing positions, each including a polish pad carried by a polishing head which is movable toward and away from said carrier table, into and out of pressing engagement with semiconductor wafers carried on said carrier table;
index means for indexing said carrier table so that a semiconductor wafer is moved from one polishing position to another; and
control means controlling said polishing heads and said index table so that a semiconductor wafer carried on said carrier table is polished by a plurality of polishing heads.
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British Search Report Under Section 17, Patents Act 1977.
Ahmed Shamim
Fitch Even Tabin & Flannery
Gulakowski Randy
SpeedFam-IPEC Corporation
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