Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-01-03
2001-07-03
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S048000, C257S203000, C257S207000, C257S210000, C257S696000, C257S698000, C257S691000, C257S686000, C257S685000, C257S692000, C257S693000
Reexamination Certificate
active
06255729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi chip package (MCP) in which first and second semiconductor chips are mounted on a same MCP substrate. In particular, the present invention relates to the MCP in which the second semiconductor chip can be diagnosed independently of the first semiconductor chip, and a method of measuring the electrical characteristics of the second semiconductor chip mounted on the MCP.
2. Description of the Related Art
In recent years, an MCP in which a CPU chip (first semiconductor chip) and an intellectual property (IP) chip (second semiconductor chip) are mounted on an MCP substrate has come to the front. The CPU chip serves as a main and pivotal control chip and configured to perform miscellaneous information processing. And the IP chip exchanges signals with the CPU chip to perform a specific function. In the MCP of this type, the number N
MCP
of pins of the MCP is limited by:
N
MCP
=N
CPU
−N
IP
(1)
Where N
CPU
is the number of pins of the CPU chip, and N
IP
is the number of pins of the IP chip. When the MCP is viewed from the outside, only the CPU chip can drive and access the IP chip. More specifically, in the conventional MCP, terminals configured such that the IP chip can directly exchanges signals with an external circuit are not formed. Therefore, in the conventional MCP, the IP chip cannot directly receive signals from the external circuit, nor CPU chip cannot directly feed signals to the external circuit without using the interconnections and internal circuitry formed on the CPU chip.
In this manner, in the conventional MCP, signals must be supplied to the IP chip through the CPU chip. Therefore, in qualification and failure analysis of mass-produced MCPs, it was complicated and troublesome tasks and very inconvenient to analyze IP chips mounted in MCPs when some failures or degradation are found. More specifically, an easy method or a convenient structure that appropriate signals are directly supplied to the IP chip, without using the paths on the CPU chip, so as to separately analyze the failure mode of the IP chip are unknown and cannot be implemented. Similarly, in commercial products, when a defective product is found, and when the IP chip in the defective MCP must be analyzed, the failure cite and failure mechanism, etc. of the IP chip cannot be independently analyzed in the conventional MCP. As a result, the failure of the IP chip cannot be precisely analyzed, and it is extremely difficult to assess the electrical behavior of the IP chip and to study the reason for the failures occurred in the IP chip. Then considerably longer time is required to diagnose and analyze the failure site and failure mechanism, etc. of the IP chip.
In particular, in order to separately measure and inspect the electrical characteristics of the IP chip, the MCP must be decapsulated so that the IP chip can be remounted on a specific lead frame designed for testing as a single chip. This procedure is a difficult operation, which requires the closest attention and sophisticated technique, and disadvantageously spends longer time. In addition, it is disadvantageous because accidents such that the IP chips are broken, fractured or damaged at the remounting stage of the IP chips onto the single chip lead frames sometimes occur.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above problems of the MCP in which first and second semiconductor chips are mounted on an MCP substrate so that the second semiconductor chip is connected only to an external circuit through the first semiconductor chip under normal usage condition.
Then the present invention has an object to provide the MCP, but having a new structure in which the second semiconductor chip can be electrically analyzed in a short time, without employing signal paths running through the first semiconductor chip, only under the specific condition, to allow analyze separately the second semiconductor chip.
It is another object of the present invention to provide the MCP having a new structure configured such that the second semiconductor chip can be electrically analyzed independently of the first semiconductor chip at “failure analysis mode”, directly supplying required signals to the second semiconductor chip from an external circuit.
It is another object of the present invention to provide a new method of measuring the electrical characteristics of a second semiconductor chip mounted in the MCP in which, when a degradation of manufacturing yield is found by the assessment of production management procedure, or when a failure or the like is found in a market usage, the defect or the failure of the second semiconductor chip can be easily analyzed in a short time.
It is still another object of the present invention to provide a new method of measuring the electrical characteristics of a second semiconductor chip mounted in the MCP, without requiring the conventional procedure of remounting the second semiconductor chip on a lead frame designed for a single chip testing, the new method being configured such that the second semiconductor chip is separately measured at “failure analysis mode” so as to prevent accidents such as fractures, deformations, or damages due to the complicated conventional remounting procedure.
In order to achieve the above object, a first feature of the present invention inheres in an MCP having: (a) an MCP substrate; (b) first and second semiconductor chips mounted on the MCP substrate; (c) MCP leads connected to perimeter of the MCP substrate; (d) MCP terminal wires for connecting the MCP leads to the first semiconductor chip; (e) interface signal wires for connecting the first and second semiconductor chips to each other; (f) a first extra bonding pad electrically connected to one of the interface signal wires; and (g) a second extra bonding pad electrically connected to one of the MCP leads and arranged near the first extra bonding pad. In this case, the connection between the MCP leads and the first semiconductor chip, the connection between the first and second semiconductor chips, or the connection between the first and second extra bonding pads may be performed by a wire bonding method, a tape automated bonding (TAB) method, or a flip chip bonding method, using solder bump (solder joint) or another conductive material bump.
In the MCP according to the first feature of the present invention, the first and second extra bonding pads may be electrically isolated from each other in a normal usage condition. The MCP has a control circuit and a structure in which the first and second extra bonding pads are electrically connected to each other in “a failure analysis mode”, by which a failure or a defect is analyzed. More specifically, the first extra bonding pad and the second extra bonding pad are connected to each other, so that signal exchange between the second semiconductor chip and an external circuit without using the first semiconductor chip. As a result, the second semiconductor chip can be electrically independently analyzed, and an easy analysis and a reduction in analysis time can be achieved.
Furthermore, in an assessment of the second semiconductor chip except for the failure analysis, the second semiconductor chip can be diagnosed without requiring a single chip package assembly for mounting the second semiconductor chip. Then, the single chip lead frame employed by conventional method is not necessary, and the cost of the MCP can be reduced.
A second feature of the present invention inheres a method of measuring electrical characteristics of an IP chip mounted on an MCP substrate so as to form an MCP. The MCP substrate has MCP terminal wires, interface signal wires, first extra bonding pads electrically connected to the interface signal wires and second extra bonding pads electrically connected to the MCP terminal wires. And the MCP substrate is connected to MCP leads on perimeter of the MCP substrate. Further, the second extra bonding pads are electrically
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Williams Alexander O.
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