Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1999-04-29
2001-08-07
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000, C257S158000, C257S159000
Reexamination Certificate
active
06271540
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating an inverted staggered type thin film transistor with a high reliability using an amorphous silicon and a structure of the thin film transistor. More particularly, the present invention relates to a method for fabricating an inverted staggered type thin film transistor with a high reliability, which can prevent an undesired back channel effect, in which a channel is turned on during an off state of the thin film transistor to cause a leakage current, and relates to a structure of the thin film transistor. Further, the present invention relates to a method for fabricating a thin film transistor which can control a threshold voltage V
Fth
of a front channel.
BACKGROUND OF THE INVENTION
Thin film transistors (TFTs) using an amorphous silicon (a-Si) have been used in a large size image sensor or in a large size liquid crystal display (LCD) since the TFTs can be formed on a large size substrate. A practical technology has been established for mounting a plurality of TFTs on a glass substrate as switching elements of picture elements (PELs) of a LCD.
The TFT is classified into a normally staggered type and an inverted staggered type depending upon the order of stacking various thin films on the substrate. In the normally staggered type TFT, a source electrode and a drain electrode are initially formed on the substrate, and a gate electrode is finally formed. In the inverted staggered type TFT, the gate is initially formed on the substrate, and the source electrode and the drain electrode are finally formed. The inverted staggered type TFT of these two types of TFTs has been frequently used in the LCD due to its easiness of fabrication and a stability of operational characteristics. In the inverted staggered type TFT, the gate electrode exists below a gate insulating film, and the source electrode and the drain electrode exist above the gate insulating film and are exposed to an external atmosphere, as shown in
FIGS. 1C
,
2
D and
3
D. Two fabrication methods of the inverted staggered type TFT are shown in the
FIGS. 1A-1C
and
2
A-
2
D.
FIGS. 1A-1C
show the fabrication method of a channel etch type TFT
1
, and the
FIGS. 2A-2D
show the fabrication method of a channel passivation type TFT
2
.
In a Japanese Published Examined Patent Application 6-9246 and a Published Unexamined Patent Application 7-114285, for example, the fabrication method of the inverted staggered type TFT of the channel etch type is described as a prior technology. In a first step (a) shown in
FIG. 1A
, a structure is prepared in which, after a gate electrode
20
is patterned on a glass substrate
10
, a gate insulating film
30
, such as a silicon oxide film or a silicon nitride film, an amorphous silicon (a-Si) layer
40
of an order of a thickness of about 2000 Å and a n+a-Si film
70
as a low resistive film are sequentially stacked. In a step (b) shown in
FIG. 1B
, the patterns of the source and drain electrodes
80
is formed. Finally, in a step (c) shown in
FIG. 1C
, a portion of the n
+
a-Si layer
70
above a back channel region
100
of the a-Si layer
40
is removed by a reactive ion etching (RIE) process using the source and drain electrodes as a mask. During this etching, an upper interface of the a-Si layer
40
is partially removed. By using this fabrication method, the TFT array for the LCD in which a plurality of TFTs
1
, as shown in the step (c), are formed is obtained.
However, a problem is caused in the fabrication method using the channel etching, that the channel region is damaged by an impact of the ions in the etching process. The impact of the ions in the etching process shown in
FIG. 1C
damages a front channel region
110
(an interface of the gate insulating film
30
/the a-Si layer
40
) and its electric characteristics, so that the stability of the TFT characteristics and a reliability of quality are degraded. To solve the damage to the front channel region
110
in the etching step (c), it can be considered to use the a-Si layer
40
of a thickness about 2000 Å. However, this thickness of the a-Si layer
40
is four or five times of a thickness (~500 Å) of an a-Si layer of a channel passivation film type TFT shown in the
FIG. 2D
, later described. Accordingly, a parasitic serial resistance having a value of several times of a contact resistance of the normal TFT exists between the source and the drain, so that a voltage normally applied to the PEL electrode can not provide a sufficient conduct characteristics during the turn on of the TFT. In the case that the channel etching type TFT
1
is used as the switching element of the LCD, a large size TFT is required to realize a sufficient write current. The use of the large size TFT in the PEL portion of the LCD causes an aperture ratio indicating a performance of the LCD to be decreased. The LCD panel comprises the area of PELs (the apertures through which the light passes) and the area of the other components. The aperture ratio is the ratio of the area of the PELS to the entire area of the LCD panel. The larger the aperture ratio is, the higher is the luminance of the display image of the LCD, so that a clear image is displayed and a large power saving effect is obtained. Usual LCD has the aperture ratio of 50~70%. In the case that the channel etching type TFT
1
is used as the switching element of the LCD, the large size TFT should be formed for each of the PELs to maintain a sufficient write current. As a result, the area of the TFT becomes large, so that the aperture ratio of the LCD panel using the TFTs is decreased.
In contradistinction to the TFT
1
fabricated by the channel etching process, the channel passivation film type TFT
2
shown in the
FIG. 2D
does not require the protection of the front channel region
110
from the damage applied in the etching process. The thickness of a-Si layer
40
of the usual channel passivation film type TFT
2
may be on the order of only about 500 Å. The thickness of the a-Si layer of the channel passivation film type TFT
2
is sufficiently thinner than the thickness of the a-Si layer of the channel etching type TFT
1
shown in the
FIG. 1C
, the problem of decreasing the aperture ratio is solved in the structure of the channel passivation film type TFT
2
. Describing the fabrication method of the channel passivation film type TFT
2
, in step (a) shown in
FIG. 2A
, a structure is prepared in which, after the gate electrode
20
is patterned on the glass substrate
10
, the gate insulating film
30
, such as the silicon oxide film or the silicon nitride film, the a-Si layer
40
may have a thickness of about 500 Å, and a silicon nitride film as a channel passivation layer
50
are sequentially stacked. In step (b) shown in
FIG. 2B
, the channel passivation layer
50
is patterned by using a resist mask pattern
60
formed above the gate electrode
20
. In step (c) shown in
FIG. 2C
, the resist mask pattern
60
is removed, and a low resistive film
70
of the a-Si doped with the N type dopants is formed on the entire surface. In final step (d) shown in
FIG. 2D
, the patterns of the source and the drain electrode
80
are formed with respect to the gate electrode
20
. A portion of the low resistive film (the n
+
a-Si)
70
above the back channel region
100
is etched by using the source and drain electrodes
80
as the mask, whereby the inverted staggered type TFT
2
in which the channel is protected by the passivation film is completed. In the Japanese Published Examined Patent Application 6-9246, one of the fabrication methods of the inverted staggered type TFT of the channel passivation film type is described.
In the channel passivation film type TFT
2
shown in the
FIG. 2D
, the channel passivation film
50
(for example the silicon nitride film) is continuously formed on the a-Si layer
40
in the step (a). When the a-Si layer
40
and the silicon nitride film
50
are continuously formed, the formation of lattice defects, to which
Miyamoto Takashi
Tsujimura Takatoshi
Abraham Fetsum
International Business Machines - Corporation
Trepp Robert M.
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