Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-09-30
2001-06-12
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S405000
Reexamination Certificate
active
06247035
ABSTRACT:
BACKGROUND
The present invention relates generally to radio communication systems and, more particularly, to the use of a modified fast convolution algorithm in channelizers and de-channelizers of a radio communication system.
In radio base station applications for cellular, Land Mobile Radio (LMR), satellite, wireless local area networks (WLANs) and other communication systems, many receiving and transmitting channels are handled simultaneously. In the future, mobile terminals, i.e. mobile telephones, will also include this capability. Such systems include digital channelization and de-channelization structures in their receivers and transmitters, respectively. Channelization and de-channelization can be defined as the filtering, decimation/interpolation and the frequency conversion of the signals transmitted and received.
The traditional receiver architecture is illustrated in FIG.
1
. In
FIG. 1
, a Radio Frequency (RF) signal is received by the antenna
105
and then downconverted to an intermediate frequency (IF) by a RF front end
110
. The RF front end
110
consists of components such as Low Noise Amplifiers (LNAs), filters and mixers. The desired channel is then extracted by the receiver channelizer
120
. The analog channelizer
120
also consists of LNAs, mixers and filters.
The desired channel is then processed at baseband by the RX baseband processing unit
130
to produce the received digital data stream. Today, baseband processing generally consists of analog-to-digital conversion, digital filtering, decimation, equalization, demodulation, channel decoding, de-interleaving, data decoding, timing extraction, etc.
The traditional transmitter architecture in
FIG. 1
is the dual of the receiver architecture. The transmitted data is first processed by the TX baseband processing unit
140
which consists of data coding, interleaving, channel coding, modulation, interpolation filtering, digital-to-analog conversion, etc. The baseband channel is then converted to an IF frequency via the transmit de-channelizer
150
. The transmit analog de-channelizer
150
consists of filters, mixers and low power amplifiers. The IF signal is then converted to RF and amplified by the RF front end
160
which consists of mixers, filters, and a high power amplifier. Finally, the signal is transmitted by the antenna
165
.
FIG. 1
illustrates the traditional architecture for a single channel receiver and transmitter of a mobile terminal (i.e., mobile phone). In the case of a base station, multiple channels are processed in a similar way. On the receiver side, the path will split at some point to form multiple paths for each channel being processed. On the transmitter side, the channels will be processed individually and then combined at some point to form a multichannel signal. The point of the split and combination varies, and therefore, a variety of base station receiver and transmitter architectures can be created. More importantly, though, the traditional analog and digital interface is currently somewhere between the channelizer and baseband processing blocks.
The analog channelizer/de-channelizer is complex to design and manufacture, and therefore costly. In order to provide a cheaper and more easily produced channelizer/de-channelizer, the future analog and digital interface will lie, instead, somewhere between the RF front end and channelizer blocks. Future radio receiver and transmitter structures of this type are called a variety of names, including multi-channel radio, wideband digital tuners, wideband radio or software radio, and they all require a digital channelizer/de-channelizer.
Efficient digital channelizer/de-channelizer structures, which perform filtering, decimation/interpolation and frequency conversion, are very important in terms of power consumption and die area on a per channel basis. One of the main goals of these structures is to integrate as many channels into a single Integrated Circuit (IC) as possible.
An efficient and flexible method of channelization is presented in copending, commonly assigned, International Patent Application No. PCT/SE99/00971, entitled “Digital Channelizer and De-channelizer,” the entirety of which is incorporated here by reference. The method disclosed therein is based upon the fast convolution algorithm, an algorithm for efficient implementation of filters using the correspondence between multiplication in the frequency (Fourier) domain and convolution in the time domain.
FIGS. 2A and 2B
illustrate the modified fast convolution algorithm applied to a channelizer and de-channelizer, respectively. In
FIG. 2A
, an input signal
205
is provided to the channelizer. The input signal
205
is a stream of data coming from a prior process, such as an ADC.
The data stream
205
is first processed by the &eegr; % overlap block generator
210
. This process is based on the amount of percentage overlap, the size of the Discrete Fourier Transform (DFT) and the type of overlap, that is overlap/add or overlap/save as discussed below. In the case of overlap and add, the data stream is chopped into non-overlapping sections of length N
DFT*
(1−&eegr;), and padded with N
DFT*
&eegr; zeros to form a single block. In the case of overlap and save the data is chopped into blocks of length N
DFT
, which have an overlap with the previous block given by a length of N
DFT*
&eegr;.
The resulting blocks are then input into the DFT algorithm. The DFT algorithm is completed in block
230
. As a result of pipeline FFT processing, the output of the FFT is not in the correct order. Therefore, the bin select and extract block
240
must compensate for this by reordering the output sequence and only selecting the bins needed. The number of bins needed depends on the number of filter coefficients
260
.
The selected bins are multiplied with the filter frequency coefficients
260
in multiplier
250
. An inverse Discrete Fourier Transform (inverse-DFT or IDFT)
270
is then completed on the result of the previous multiplication.
The output of the IDFT is inserted into the &eegr; % overlap block combiner
280
. The combination operation depends on the % overlap of the blocks and whether an overlap/save or an overlap/add is being employed. For either overlap and add or overlap and save, the blocks are overlapped with the previous block by a length equal to N
IDFT*
&eegr;. For overlap and add, the overlapping part of the block is added to the previous block's corresponding overlapping part, while for overlap and save the overlapping part of the block is simply discarded. For both overlap and add and overlap and save there are no operations performed on the non-overlapped part of the block.
FIG. 2B
illustrates the modified fast convolution algorithm as applied to a de-channelizer. The input signal is a stream of data
202
coming from a prior process, such as an ADC operation. In contrast to
FIG. 2A
, the input data stream is specific to one channel, rather than a stream combining many channels.
The data stream
202
is first processed by the &eegr; % overlap block generator
204
. This process is largely based on the amount of percentage overlap, the size of the DFT and the type of overlap, that is overlap/add or overlap/save. In the case of overlap and add, the data stream is chopped into nonoverlapping sections of length N
DFT*
(1−&eegr;), and padded with N
DFT*
&eegr; zeros to form a single block. In the case of overlap and save the data is chopped into blocks of length N
DFT
, which have an overlap with the previous block given by a length of N
DFT*
&eegr;.
A Discrete Fourier Transform (DFT)
206
is then completed on the result of the previous operation. One skilled in the art will appreciate that the DFT
206
could, in the alternative, be implemented as an FFT. As contrasted with the receiver in
FIG. 2A
, the DFT
206
structure is small and the IDFT
216
structure is large, the opposite of the receiver.
The block is then multiplied by multiplier
208
with filter frequency coefficients
212
. The frequency filter coefficients
212
are equ
Burns Doane Swecker & Mathis L.L.P.
Mai Tan V.
Telefonaktiebolaget LM Ericsson (publ)
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