Amplifiers – With semiconductor amplifying device – Including particular power supply circuitry
Reexamination Certificate
1999-11-18
2001-05-22
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular power supply circuitry
C330S267000, C323S314000
Reexamination Certificate
active
06236273
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to power amplifiers and more particularly to high-power, monolithic, integrated circuit (IC) power amplifiers.
2. Background Art
Certain telecommunications standards have been developed in the United States to provide high-speed digital access between customers and a central office. One example is the Asymmetric Digital Subscriber Loop (ADSL) standard, which provides a data rate of approximately 6 Mb in the direction from the central telephone office to the customer. As a result of the high data rate, ADSL has become one of the preferred standards for supplying, for example, Internet service over a standard copper wire twisted pair.
Although it offers a high data rate, the ADSL standard requires that the line-driving amplifier at the central office be able to supply a signal of approximately 20 dBm (power with respect to a reference level of 1 mW) in power with a peak-to-rms average voltage ratio (PAR) of 5.33:1. In order to accommodate the required power output level and PAR, two line-driving amplifiers, or a line-driver pair, are commonly used in a bridge configuration with a 1:2 step-up transformer between the amplifiers and the line.
One disadvantage of this conventional arrangement is its need for power as the number of customers grows. In the near future, for example, it is expected that several thousand customers may require ADSL service from the same central office. The possibility of expending several kilowatts of power just to operate the ADSL lined rivers has therefore become a major concern regarding this type of digital service. Much research effort has therefore been applied to the problem of increasing the efficiency of monolithic, integrated circuit (IC) power amplifiers for ADSL applications.
In one known circuit arrangement, the output stage of an operational amplifier is connected to an approximately constant supply voltage, whose supply voltage is greater in magnitude than the maximum zero-to-peak output voltage. The amount by which the supply voltage exceeds the maximum output voltage is commonly known as the voltage headroom required for the stage. For example, a typical value for the voltage headroom in prior art circuits is 3V. The zero-to-peak voltage for an ADSL amplifier in the central office is approximately 8.42V. The minimum power supply voltage for such an arrangement would therefore be approximately 11.42V. The supply voltage, given some initial voltage setting inaccuracy, may therefore be nominally 12V.
Because the average current required from each power supply (+/−12V) in the amplifier pair is approximately 28.5 mA for the ADSL central office, the minimum power possible for a 12V supply would be 4×12V×28.5 mA=1.36 W. This would be the minimum power given ideal “Class C” operation of the output stage and without providing additional power for any amplifier current bias circuits. Because ADSL power amplifiers require low output distortion—typically better than 70 dB for signal to noise-and-distortion ratios—“Class C” operation is not practical. It is therefore understandable why, despite considerable efforts, it has not been possible to reduce power consumption for ADSL central office line driving amplifier pairs significantly below 1.5 W. Similar problems of course arise, or may arise, even in systems that use standards other than the ADSL for enabling data exchange between some central system and a number of customers or other client systems large enough that it becomes advantageous to reduce the need for supply power to the various amplifiers.
What is needed is therefore an arrangement that would make possible a reduction in the power level for the amplifier arrangement as much as possible, and preferably to below 1.0 W, especially for systems following the ADSL standard. This invention provides such an arrangement.
SUMMARY OF THE INVENTION
A monolithic integrated circuit amplifier according to the invention has an input signal and an output signal, as well as a gain stage. The gain stage has a gain stage output signal and, as an input, the amplifier input signal. A buffer stage produces an amplifier output signal and has, as its input signal, the gain stage output signal. An output stage, included within the buffer stage, has at least a first power output transistor.
First and second voltage supplies are included, the second voltage supply having a relatively higher magnitude than the first. A first power control circuit is connected to both the first and second voltage supplies, and to the output stage through a regulator bus. The first power control circuit includes first and second switching means connected to the first and second voltage supplies, respectively. Outputs of the first and second switching means are both connected to the regulator bus; these outputs are preferably the emitters (or MOS equivalents) of respective first and second analog switching transistors.
When an output demand voltage is less than a predetermined switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply via the first switching means and the regulator bus. When the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply, via the second switching means and the regulator bus.
According to one aspect of the invention, voltage at the collector (or MOS equivalent) of the output transistor is maintained greater than the voltage at the emitter (or MOS equivalent) of the output transistor by a predetermined, substantially constant amount.
According to another aspect of the invention, when the first switching means is conducting and supplying the current to the output stage, the voltage on the regulator bus itself blocks current output from the second switching means.
According to yet another aspect of the invention, a first and a second control transistor are included in the first and second switching means, respectively. Voltage clamping means is then preferably also provided for limiting a maximum voltage on the base of the first control transistor. This limits the maximum voltage on the base of the first analog switching transistor, and thereby also substantially prevents the flow of reverse current through the emitter and collector of the first analog switching transistor.
According to still another aspect of the invention, voltage headroom circuitry is also provided for setting a voltage headroom, that is, the lowest voltage constantly available at the second current terminal of the output transistor relative to the first current terminal of the output transistor.
The preferred embodiment of the invention also includes voltage difference-setting circuitry, the voltage difference being defined as the difference between the voltage available at the second current terminal of the output transistor relative to the first current terminal of the output transistor in a first condition and a second condition. The first condition is when the voltage is being provided by current from the first analog switching transistor and the second condition is when the voltage is being provided by current from the second analog switching transistor.
In the preferred embodiment of the invention, the first and second voltage supplies comprise a first dual voltage supply. The regulator bus connecting the first dual voltage supply to the output stage via the first power control circuit is thereby a first regulator bus. The amplifier then preferably further comprises a second dual voltage supply, including third and fourth voltage supplies having the same amplitudes but opposite polarity relative to the first and second voltage supplies, respectively; and a second power control circuit having the substantially identical components and connections but opposite polarities relative to the first power control circuit. The invention then further includes, in the buffer stage, a common output voltage terminal for both power con
Pairgain Technologies, Inc.
Shingleton Michael B
Slusher Jeffrey
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