Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-01
2001-06-12
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S733000, C438S734000, C438S738000
Reexamination Certificate
active
06245685
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a square oxide structure or a square floating gate structure without a rounding effect at the corners of the square oxide structure or the square floating gate structure.
2) Description of the Prior Art
The use of a silicon nitride layer as an oxidation mask is well known. To form square structures, such as oxide isolation structures or floating gates in a split cell memory, a photosensitive mask is formed with square openings, and the silicon nitride layer is etched through these openings.
However, due to limitations of the photolithography process, the corners of square openings in the photosensitive mask become rounded. This rounding of the corners of a square opening in a photosensitive mask is known as a rounding effect. As device dimensions continue to shrink, this rounding effect at the corners of square structures can have a detrimental effect on device performance. This detrimental effect can be worse when mis-alignment between photolithography masks occurs.
Another problem which occurs as packing density increases, is that the gap between floating gates in a split cell memory device is limited by the photolithography process. After a polysilicon layer is formed, openings (or gaps) are etched to define and separate floating gates. The width of the opening in the photosensitive or silicon nitride etch mask is limited by parameters of the photolithography process such as wavelength of the energy source, resolution, and aspect ratio.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,879,992 (Hsieh et al.) shows a flash split gate memory using a poly oxide hard mask to etch an underlying floating gate in an underlying polysilicon layer.
U.S. Pat. No. 5,858,940 (Hsieh et al.) discloses a flash cell split gate memory using a poly oxide hard mask with a sharp tip for etching a floating gate in an underlying polysilicon layer.
U.S. Pat. No. 5,780,341 (Ogura) shows a method for forming an EPROM having an STI.
U.S. Pat. Nos. 5,364,806 (Ma et al.) and 5,811,853 (Wang) disclose other methods for forming flash split gate memories.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a square oxide structure without a rounding effect at its corners.
It is another object of the present invention to provide a method for forming a square floating gate in a split-gate cell without a rounding effect at its corners.
It is yet another object of the present invention to provide a method for forming square floating gates in a split-gate cell with a reduced gap width therebetween.
To accomplish the above objectives, the present invention provides a method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. The key to the invention is the formation of a second dielectric layer and a photosensitive mask having openings perpendicular to each other.
The process begins by providing a semiconductor structure having a pad layer thereon for a square oxide structure or a semiconductor structure having a gate oxide layer and a polysilicon layer successively formed thereover for a floating gate. A first dielectric layer is formed on the pad layer or the polysilicon layer, and a Second dielectric layer is formed on the first dielectric layer. A first photosensitive mask is formed, the Second dielectric layer is patterned to form parallel openings in a first direction, and the first photosensitive mask is removed. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the Second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the Second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the TEOS oxide are removed. The square oxide structure is completed by etching a trench in the semiconductor structure and forming an STI or LOCOS. The square floating gate is completed by growing polysilicon oxide structures in the square openings in the first dielectric layer to form a plurality of square polysilicon oxide hard masks with a pattern of openings therebetween, and etching the polysilicon layer through the pattern of openings between the polysilicon oxide hard masks forming square floating gate polysilicon regions under the polysilicon oxide hard masks.
The present invention provides considerable improvement over the prior art. The key advantage of the present invention is that the two separate, perpendicular masks used to form a square opening reduce the rounding effect that occurs due to the photolithography process. The present invention provides square structures without rounded corners, thereby inproving device performance, especially when mismatch occurs.
Also, because the polyoxide hard mask formed in accordance with the present invention grows in width by the length of the bird's beaks which form during oxidation, the gap can be reduced by two times the length of the birds beak.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5364806 (1994-11-01), Ma et al.
patent: 5780341 (1998-07-01), Ogura
patent: 5811853 (1998-09-01), Wang
patent: 5858840 (1999-01-01), Hsieh et al.
patent: 5879992 (1999-03-01), Hsieh et al.
patent: 5939741 (1999-08-01), Clampitt et al.
Hsieh Chia-Ta
Kuo Di-Son
Sung Hung-Cheng
Ackerman Stephen B.
Powell William
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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