Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-08-09
2001-01-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S689000, C438S690000, C438S691000, C438S692000
Reexamination Certificate
active
06180527
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to articles and methods of thinning articles, in particular, integrated circuit wafers, as well as apparatuses and systems suitable for carrying out such methods.
BACKGROUND OF THE INVENTION
In many known methods for manufacturing semiconductor chips, a relatively large wafer, for example, of silicon is used as a starting material. Such wafers can be obtained by slicing a crystal ingot to a suitable thickness to obtain a number of nearly disk-shaped semiconductor wafers. Typically, both surfaces of each wafer are subjected to abrasive machining, followed by etching in a suitable mixed acid solution, after which one surface of each wafer is polished to obtain a mirror surface. Circuits are applied to the mirror surface of the resulting semiconductor wafer by known processing steps of printing, etching, diffusion, doping, etc.
In the methods described above, the silicon wafers are sliced from the crystal ingot to a thickness that is greater than desirable for a finished integrated circuit product so as to provide a more robust wafer to stand up to the rigors of the integrated circuit fabrication processes. Particularly, relatively thick silicon wafers are necessary during the integrated circuit fabrication steps to prevent warpage and breakage of the wafer as a result of certain heating, handling and other circuit fabrication processes. After the integrated circuits have been fabricated, it is desirable to reduce the thickness of the wafer in order to reduce the overall size and mass of the finished product.
U.S. Pat. No. 5,223,734 discloses a gettering process for semiconductor manufacturing. The gettering process is performed after device formation and after a protective layer such as borophosphorus silicate glass (BPSG) or phosphorous silicate glass (PSG) has been applied to the front side of a semiconductor wafer. The gettering process includes thinning and roughening a backside of the wafer using chemical mechanical planarization (CMP), depositing and diffusing a gettering agent such as phosphorus into the backside of the wafer. The wafer can then be annealed for driving in the gettering agent and segregating mobile contaminants in the wafer at gettering centers formed at the dislocations and at gettering agent sites within the wafer crystal structure. The annealing step may also function to reflow and planarize the BPSG or PSG protective layer. As optional steps, the front side of the wafer may be chemically mechanically planarized (CMP) to planarize the protective, BPSG layer, prior to depositing and diffusing the gettering agent into the backside of the wafer. Additionally, as another optional step, the front side of the wafer may be chemically mechanically planarized (CMP) after the annealing step, if required, to further planarize the protective (BPSG) layer.
U.S. Pat. No. 5,851,845 (Farnworth) discloses a method for packaging a semiconductor die. The package includes a thinned die mounted on a compliant adhesive layer to a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. Either a wet or dry etching process can be used to etch the backside of the wafer.
U.S. Pat. No. 5,895,972 discloses thinning a silicon semiconductor substrate by etching, polishing, milling, etc.
Despite these and other efforts, there remains a need for techniques which enable the manufacture of products with ever-increasing degrees of precision, and with ever-decreasing size, without sacrificing or compromising required properties.
SUMMARY OF THE INVENTION
According to the present invention, there are provided methods, articles and apparatus which, as discussed in more detail below, allow for manufacture of a variety of articles, e.g., IC products, with increased precision, reduced likelihood of damage during manufacture, and further reduction in size and mass.
According to the present invention, a method of thinning an article comprises applying a layer to a first surface of the article. A layer is then formed by removing a portion of the reference layer using a second surface of the article which is opposite to the first reference surface as a plane of reference, to provide a reference surface on the reference surface. Preferably, the reference surface is parallel to the second surface. The article is thinned by removing a portion of the second surface of the article to provide a thinned surface using the reference surface as a plane of reference. By using the reference surface as a plane of reference, the thinned surface is provided with a predetermined specific orientation relative to the reference surface, preferably a parallel orientation.
After thinning, the reference layer can be removed, if desired. Therefore, in one aspect of the invention, the reference layer can be a “sacrificial” layer. In another aspect of the invention, a portion of the reference layer, i.e., some or all of the portion remaining after forming the reference surface, can remain and become part of the finished product.
In accordance with the present invention, the article can be thinned with greater accuracy, because the orientation of the thinned surface is reliably controlled by virtue of the process of the invention, which creates a reference surface having a predetermined orientation relative to the second surface, which reference surface is preserved and used as a reference when thinning the article to produce the thinned surface.
The article can be a single layer, e.g., a silicon wafer, prior to device formation thereon, or it can comprise any number of layers, and can optionally include one or more elements, e.g., semiconductor devices, formed in or on any of the layers. In either case, the reference layer is applied to the first surface of the article.
In one aspect of the invention, the reference layer is preferably a polymer which is coated as a liquid onto the first surface of the article, and allowed to cure on its own or with the help of a curing process and/or agent. Alternatively, the reference layer can be applied as a solid layer, and optionally adhered to the article using an adhesive.
In a preferred aspect of the present invention, the article is an assembly made in the course of manufacturing an IC device. For example, one application of the invention is the thinning of a wafer on which a plurality of semiconductor devices have been formed. In accordance with this preferred aspect of the invention, the article referred to above comprises a wafer having at least first and second surfaces, with the semiconductor devices being formed on the first surface and/or in the wafer, and with the reference layer being applied to the first surface, such that the semiconductor devices are positioned between the wafer and the reference layer.
These and other features and advantages of the invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention which is provided in conjunction with the accompanying drawings. The invention is not limited to the exemplary embodiments described below and it should be recognized that the invention includes all modifications falling within the scope of the attached claims.
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Farnworth Warren M.
Gochnour Derek J.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Lee Granvill
Micro)n Technology, Inc.
Smith Matthew
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