Semiconductor topography employing a nitrogenated shallow...

Details Semiconductor topography employing a nitrogenated shallow... Semiconductor topography employing a nitrogenated shallow...

1998-10-21

2001-04-17

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S501000, C257S506000, C257S508000, C257S510000, C257S513000, C438S459000

Reexamination Certificate

active

06218720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for forming an integrated circuit containing an improved isolation structure.
2. Description of the Related Art
The fabrication of an integrated circuit involves the formation of numerous devices within active areas of a semiconductor substrate. Isolation structures are needed to electrically isolate one device from another. Isolation structures define the field regions of the semiconductor substrate, and the device areas define the active regions. The devices may be interconnected with conducting lines running over the isolation structures.
A popular isolation technology used in the fabrication of integrated circuits involves locally oxidizing silicon. In local oxidation of silicon (“LOCOS”) processes, an oxide layer is first grown upon a silicon substrate. A silicon nitride (“nitride”) layer is deposited upon the oxide layer. The oxide layer serves as a pad layer for a nitride layer. The surface of a field region of the silicon substrate is then exposed by etching portions of the nitride layer and oxide layer above this region. Active regions of the silicon substrate remain covered by the nitride layer, which is used as a mask to prevent oxidation of these regions in subsequent steps. An implant is performed in the field region to create a channel-stop doping layer. The exposed portion of the silicon substrate within the field region is then oxidized. The silicon dioxide (“oxide”) grown in the field region is termed field oxide. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing can help to prevent the establishment of parasitic channels in the field regions.
Although LOCOS has remained a popular isolation technology, the basic LOCOS process described above has several problems. When growing the field oxide, oxide growth should ideally be contained within the field region. In reality, however, some oxide growth may occur in a lateral direction, causing the field oxide to grow under and lift the edges of the nitride layer. Because the shape of the field oxide at the nitride edges is that of a slowly tapering wedge that merges into the pad oxide, the wedge is often described a bird's beak. In many instances, formation of the bird's beak can cause unacceptable encroachment of the field oxide into the active regions. In addition, the high temperatures associated with field oxide growth often cause the pre-implanted channel-stop dopant to migrate towards adjacent active regions. An increase in the dopant concentration near the edges of the field oxide can create a reduction in the drain current, an outcome that is often described as the narrow-width effect. Furthermore, thermal oxide growth is significantly less in small field regions (i.e., field areas of narrow lateral dimension) than in large field regions. Because of this reduction in oxide growth, an undesirable phenomenon known as the field-oxide-thinning effect may occur in small field regions. Field-oxide-thinning can produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Despite advances made to decrease the bird's beak, channel-stop encroachment and non-planarity problems, it appears that LOCOS technology is still inadequate for deep submicron technologies. Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as shallow trench isolation (“STI”).
An isolation structure formed by a conventional shallow trench isolation process (hereinafter “the conventional STI process”) is shown in FIG.
1
. Silicon substrate
100
is typically a lightly doped wafer of single crystal silicon. The conventional STI process includes an initial step in which a relatively shallow trench (e.g., between 0.3 and 0.5 microns in depth) is etched in silicon substrate
100
. The trench is then filled with trench dielectric
102
, which is usually a deposited oxide. Some trench processes also include an intermediate step of growing oxide on the trench floor and sidewalls before filling the trench with trench dielectric
102
. After the trench is filled, the upper surface of trench dielectric
102
is then made coplanar with the upper surface of silicon substrate
100
to complete the isolation structure.
The conventional STI process eliminates many of the problems of LOCOS techniques, including bird's beak and channel-stop dopant redistribution. STI processes are also better suited than LOCOS processes for isolating densely spaced active devices having field regions less than one &mgr;m wide. In addition, the trench isolation structure formed in STI processes is fully recessed, offering at least the potential for a planar surface. Moreover, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process. But despite its many advantages over LOCOS techniques, the conventional trench isolation process described above nevertheless has its own set of drawbacks.
One problem common to isolation structures, including those formed by the conventional STI process, is the unwanted diffusion of foreign species into the trench dielectric. For example, dopants implanted into active areas within semiconductor substrate
100
and adjacent to the trench can migrate into trench dielectric
102
during heat processing steps. Because of the fast diffusion rate of boron through silicon, boron diffusion into trench dielectrics is particularly widespread. Unfortunately, the voltage required to cause dielectric breakdown of a STI isolation structure generally decreases as the dopant density within the isolation structure increases. Consequently, when a voltage is applied across a conductor arranged horizontally above the trench isolation structure, dielectric breakdown may occur in those areas of the isolation structure having a high dopant density.
Another drawback of the conventional STI process results from the formation of sharp upper corners
106
near the surface of semiconductor substrate
100
. Sharp corners are those defined by a sidewall surface (or perimeter) of the trench near the top of the trench that are substantially perpendicular to the substrate upper surface. Sharp upper corners
106
are typically a result of the highly directional etch used to form the trench.
Sharp upper comers
106
may introduce certain undesirable effects during subsequent processing steps that can influence an integrated circuit's operation. One problem that results from sharp upper comers
106
is the production of structural stresses in the crystal structure of substrate
102
when subsequent layers are deposited over and into a previously defined trench. The structural stresses are caused by stress mismatches between the substrate bulk material (a single crystal lattice) near the edge of the active area and the overlying dielectric or conductive layers placed proximate to the active area edge or periphery. Any stress within the lattice may cause a number of dislocations in the silicon crystal near and around upper corners
106
. These dislocations usually migrate deeper into lower portions of the substrate during subsequent thermal processing steps (e.g., annealing). As these dislocations migrate away from sharp upper corners
106
, the dislocations may form convenient paths for leakage currents. Consequently, the dislocations may provide an electrical conduction bridge that allows currents flowing through one device to “leak” into a neighboring device.
In further processing, a dielectric layer
110
is typically deposited over the planarized surface. As shown, a conductive pattern
108
may be deposited and patterned over dielectric layer
110
. Conductive pattern
108
may be a metal line used as an electrical interconnection between devices, or alternatively, a polysilicon line used in transistor gates. Sharp upper corners

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